検索結果5件中 1-5 を表示

  • Yasushi Tateshita ID: 9000019322502

    Device Technology Department, Semiconductor Technology Development Division, Semiconductor Business Group Consumer Products & Devices Group, Sony Corporation, 4-14-1 Asahi-cho, Atsugi, Kanagawa 243-0014, Japan (2010年 CiNii収録論文より)

    CiNii収録論文: 1件

    • Planar Metal–Oxide–Semiconductor Field-Effect Transistors with Raised Source and Drain Extensions Fabricated by In situ Boron-Doped Selective Silicon Epitaxy (2010)
  • Tateshita Yasushi ID: 9000019414848

    Device Technology Department, Semiconductor Technology Development Division, Semiconductor Business Group Consumer Products & Devices Group, Sony Corporation, 4-14-1 Asahi-cho, Atsugi, Kanagawa 243-0014, Japan (2010年 CiNii収録論文より)

    CiNii収録論文: 1件

    • Novel Damascene Gate Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated by In situ Arsenic- and Boron-Doped Epitaxy (2010)
  • Tateshita Yasushi ID: 9000019432347

    Semiconductor Technology Development Division, Semiconductor Business Group, Sony Corporation, 4-14-1 Asahi-cho, Atsugi, Kanagawa 243-0014, Japan (2008年 CiNii収録論文より)

    CiNii収録論文: 1件

    • Tinv Scaling and Gate Leakage Reduction for n-Type Metal Oxide Semiconductor Field Effect Transistor with HfSix/HfO2 Gate Stack by Interfacial Layer Formation Using Ozone–Water-Last Treatment (2008)
  • Tateshita Yasushi ID: 9000019471196

    Semiconductor Technology Development Division, Semiconductor Business Group, Sony Corporation, 4-14-1 Asahi-cho, Atsugi, Kanagawa 243-0014, Japan (2008年 CiNii収録論文より)

    CiNii収録論文: 1件

    • Threshold Voltage Modulation Technique using Fluorine Treatment through Atomic Layer Deposition TiN Suitable for Complementary Metal–Oxide–Semiconductor Devices (2008)
  • 舘下 八州志 ID: 9000006192656

    ソニー(株) 半導体事業グループテクノロジー開発本部 (2006年 CiNii収録論文より)

    CiNii収録論文: 2件

    • 32nmノードMOSFETのための非対称 Raised Source/Drain Extension 構造の提案 : 究極のプレーナーMOSFET (2006)
    • 32nmノードMOSFETのための非対称 Raised Source/Drain Extension 構造の提案 : 究極のプレーナーMOSFET (2006)
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