Search Results:　 1-20 of 37

Ohue Eiji , Oda Kastuya , Hayami Reiko , Washio Kastuyoshi , Shimamoto Hiromi

… W_<epi>の最適化の結果、ECLゲート遅延時間=5.3ps、スタティック型分周器の最高動作周波数=71GHzを達成した。 …

IEICE technical report. Electron devices 101(550), 71-76, 2002-01-10

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SHIMAMOTO Hiromi , ONAI Takahiro , OHUE Eiji , TANABE Masamichi , WASHIO Katsuyoshi

… By using the SMI technology and optimizing the depth of the emitter and the link base, we achieved the maximum oscillation frequency of 80 GHz, a minimum gate delay in an ECL of 11.6 ps, and the minimum noise figure of 0.34 dB at 2 GHz, which are the highest performances among those obtained from ion-implanted base Si bipolar transistors, and are comparable to those of SiGe base heterojunction bipolar transistors. …

IEICE transactions on electronics E82-C(11), 2007-2012, 1999-11-25

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ITO Shuji , NAKAMURA Toshiyuki , HOGA Hiroshi , NISHIKAWA Satoshi , FUJIMAKI Hirokazu , HIJIKATA Yumiko , OKITA Yoshihisa

… The fabricated HBT with a 12-27% graded Ge profile demonstrates a maximum cutoff frequency of 88 GHz, a maximum oscillation frequency of 65 GHz, and an ECL gate delay time of 13.8 ps. …

IEICE transactions on electronics E82-C(3), 526-530, 1999-03-25

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Hashimoto T. , Kikuchi T. , Ohashi N. , Saito T. , Wada S. , Shima A. , Kondo M. , Homma T. , Watanabe K.

… 本プロセスを用いて9Mbit0.6nsのオンチップcashを搭載した200Kゲート25psのECLゲートアレーテストチップの試作に成功した。 …

IEICE technical report. Electron devices 98(517), 83-89, 1999-01-20

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Tanabe Masamichi , Ohue Eiji , Oda Katsuya , Hayami Reiko , Washio Katsuyoshi

Proceedings of the Society Conference of IEICE 1998年.エレクトロニクス(2), 88, 1998-09-07

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ONOZAWA Akira , KITAZAWA Hitoshi , KAWAI Kenji

… In this paper, a post-layout optimization technique for power dissipation and timing of cell-based Bipolar ECL LSIs is proposed. … An ECL LSI can operate at a frequency of a few GHz but the power dissipation is very high compared to CMOS LSIs, which makes the systems using ECL quite expensive. … Therefore it is crucial to develop CAD techniques that minimize the power dissipation of an ECL LSI without decreasing its performance. …

IEICE transactions on fundamentals of electronics, communications and computer sciences E79-A(6), 892-899, 1996-06-25

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Sasaki Nagisa , Sato Hisayasu , Ueda Kimio , Mashiko Koichiro , Shibata Hiroshi

… We propose a directly controlled emitter-follower circuit with a feedback type level stabilizer for low-voltage, low-power and high-speed bipolar ECL circuits. … At a power consumption of 1 mW/gate, the new circuit is 45% faster under the loaded condition (FO=1, CL=0.5 pF) and has 47% better load driving capability than conventional ECL gates. …

IEICE transactions on electronics E78-C(4), 374-380, 1995-04-25

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Kobayashi Kazumasa , Yamano Kouji , Kokubun Hideki , Kobayashi Kiichi

差集合巡回符号の一種である(1057,813)符号を50MHzで符号化, 復号化するLSIを開発した。本LSIは、パイプライン化誤り判定回路のための復号法である修正しきい値復号法に基づいて設計されており、1μmCMOSゲートアレイで試作されている。また、その誤り訂正能力の評価方法について検討し、(a)疑似ランダム系列を用いた高速評価ボードによる誤り訂正能力の動的測定と、(b)(1057,813)符 …

Technical report of IEICE. ICD 94(204), 33-40, 1994-08-26

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Shin Hyun J.

… Simulation results based on a 0.5-μm advanced Si-bipolar technology show that the pull-down delay and drive capability of a loaded 1-mW feedback-controlled pull-down ECL gate are improved to the pull-up levels, 2.7 and 10 times better than those of the conventional resistor-pull-down ECL circuit, respectively. …

IEICE transactions on electronics E77-C(5), 853-858, 1994-05-25

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