CiNii Articles

1

Experiments for Construction of CPU on breadboards- Construction of the CPU "Revised TD4" - [in Japanese]

Kumamaru Norio , Kuroki Yoshimitu , Oda Mikio , Matsushima Norihiro , Tanaka Yoshinori , Terao Shinji

… The revised TD4 utilizes SRAM instead of the DIP switches because the formerneeds less wires and a narrower space than the latter. …

Japanese colleges of technology education journal (36), 229-234, 2013-03-00
2

Challenges to Top-Level Circuit Conferences : Experiences of Former Device Researcher [in Japanese]

宮地幸祐

電子情報通信学会技術研究報告 : 信学技報 112(365), 139-143, 2012-12-17
3

A Stable Chip-ID Generating Physical Uncloneable Function Using Random Address Errors in SRAM [in Japanese]

藤原英弘 , 藪内誠 , 塚本康正 [他]

電子情報通信学会技術研究報告 : 信学技報 112(365), 91-95, 2012-12-17
4

Invited Talk : High-performance STT-MRAM and Its Integration for Embedded Cache Memory [in Japanese]

杉井寿博 , 射場義久 , 青木正樹 [他]

電子情報通信学会技術研究報告 : 信学技報 112(365), 17-20, 2012-12-17
5

Analytical Modeling of Read Margin Probability Distribution Function of Static Random Access Memory Cells in Presence of Process Variations and Negative Bias Temperature Instability Effect

Afzal Behrouz , Afzali-Kusha Ali , Pedram Massoud

… In this work, we present an analytical model for calculating the read margin of static random access memory (SRAM) cells as a function of different transistors parameters. …

Jpn J Appl Phys 51(11), 114301-114301-9, 2012-11-25

The Japan Society of Applied Physics
6

Nonvolatile Power-Gating Field-Programmable Gate Array Using Nonvolatile Static Random Access Memory and Nonvolatile Flip-Flops Based on Pseudo-Spin-Transistor Architecture with Spin-Transfer-Torque Magnetic Tunnel Junctions

Yamamoto Shuu'ichirou , Shuto Yusuke , Sugahara Satoshi

… The circuit employs nonvolatile static random memory (NV-SRAM) cells and nonvolatile flip-flops (NV-FFs) as the storage circuits of the NVPG-FPGA. … The circuit configuration and microarchitecture are compatible with SRAM-based FPGAs, and the additional nonvolatile memory functionality makes it possible to execute efficient power gating (PG). …

Jpn J Appl Phys 51(11), 11PB02-11PB02-5, 2012-11-25

The Japan Society of Applied Physics
7

CMOS Op-amp Circuit Synthesis with Geometric Programming (画像工学)

ZHANG Yu , DONG Qing , 中武繁寿 [他]

電子情報通信学会技術研究報告 : 信学技報 112(248), 77-82, 2012-10-18
8

CMOS Op-amp Circuit Synthesis with Geometric Programming (集積回路)

ZHANG Yu , DONG Qing , 中武繁寿 [他]

電子情報通信学会技術研究報告 : 信学技報 112(247), 77-82, 2012-10-18
9

CMOS Op-amp Circuit Synthesis with Geometric Programming (信号処理)

ZHANG Yu , DONG Qing , 中武繁寿 [他]

電子情報通信学会技術研究報告 : 信学技報 112(246), 77-82, 2012-10-18
10

CMOS Op-amp Circuit Synthesis with Geometric Programming (VLSI設計技術)

ZHANG Yu , DONG Qing , 中武繁寿 [他]

電子情報通信学会技術研究報告 : 信学技報 112(245), 77-82, 2012-10-18
11

Associativity-Variable Cache to Adaptively Expand Operating Voltage Margin [in Japanese]

JUNG Jinwook , NAKATA Yohei , OKUMURA Shunsuke , KAWAGUCHI Hiroshi , YOSHIMOTO Masahiko

電子情報通信学会技術研究報告. ICD, 集積回路 111(388), 55-60, 2012-10-12

References (11)
12

A Statistical Timing Generating Circuit for Ultra-low Voltage SRAMs(News Analysis) [in Japanese]

川村卓也

The Journal of the Institute of Electronics, Information, and Communication Engineers 95(10), 943-944, 2012-10-01

CiNii Fulltext PDF - Limited
13

Static noise margin and energy performance analyses of a nonvolatile SRAM cell using pseudo-spin-MOSFET [in Japanese]

周藤悠介 , 山本修一郎 , 菅原聡

電子情報通信学会技術研究報告 : 信学技報 112(170), 65-70, 2012-08-02
14

Self-Improvement of Cell Stability in SRAM by Post Fabrication Technique [in Japanese]

Kumar Anil , 更屋拓哉 , 宮野信治 [他]

電子情報通信学会技術研究報告 : 信学技報 112(170), 13-16, 2012-08-02
15

A 40-nm 256-Kb Sub-10pJ/Access 8T SRAM with Read Bitline Amplitude Limiting (RBAL) Scheme [in Japanese]

吉本秀輔 , 寺田正治 , 梅木洋平 [他]

電子情報通信学会技術研究報告 : 信学技報 112(170), 7-12, 2012-08-02
16

Variation-Aware Low-Voltage Set-Associative Cache with Mixed-Associativity [in Japanese]

鄭晋旭 , 中田洋平 , 奥村俊介 [他]

電子情報通信学会技術研究報告 : 信学技報 112(170), 1-6, 2012-08-02
17

Static noise margin and energy performance analyses of a nonvolatile SRAM cell using pseudo-spin-MOSFET [in Japanese]

周藤悠介 , 山本修一郎 , 菅原聡

電子情報通信学会技術研究報告 : 信学技報 112(169), 65-70, 2012-08-02
18

Self-Improvement of Cell Stability in SRAM by Post Fabrication Technique [in Japanese]

Kumar Anil , 更屋拓哉 , 宮野信治 [他]

電子情報通信学会技術研究報告 : 信学技報 112(169), 13-16, 2012-08-02
19

A 40-nm 256-Kb Sub-10pJ/Access 8T SRAM with Read Bitline Amplitude Limiting (RBAL) Scheme [in Japanese]

吉本秀輔 , 寺田正治 , 梅木洋平 [他]

電子情報通信学会技術研究報告 : 信学技報 112(169), 7-12, 2012-08-02
20

Variation-Aware Low-Voltage Set-Associative Cache with Mixed-Associativity [in Japanese]

鄭晋旭 , 中田洋平 , 奥村俊介 [他]

電子情報通信学会技術研究報告 : 信学技報 112(169), 1-6, 2012-08-02

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