Search Results:　 1-20 of 988

1

Ultraviolet Photodetectors Using Transparent Gate AlGaN/GaN High Electron Mobility Transistor on Silicon Substrate

Narita Tomotaka , Wakejima Akio , Egawa Takashi

… In this paper, UV photoconductivity of a transparent gate AlGaN/GaN high electron mobility transistor (HEMT) on a Si substrate is demonstrated. … The transparent gate enables the HEMT to standby under pinch-off conditions for operation as a photodetector. … Therefore, the device can overcome the drawback of high standby-current in conventional metal gate field-effect transistor (FET)-based photodetectors without sacrificing its high responsivity. …

Jpn J Appl Phys 52(1), 01AG06-01AG06-4, 2013-01-25

The Japan Society of Applied Physics
2

Oxidation Rate Reduction of Ge with O2 Pressure Increase

Lee Choong Hyun , Tabata Toshiyuki , Nishimura Tomonori , Nagashio Kosuke , Toriumi Akira

… Furthermore, the equivalent oxide thickness = 1.2 nm of GeO2/Ge stack with excellent gate leakage current properties has been achieved by this method. …

Applied Physics Express 5(11), 114001-114001-3, 2012-11-25

The Japan Society of Applied Physics
3

Hot-Electron-Induced Device Degradation during Gate-Induced Drain Leakage Stress

Kim Kwang-Soo , Han Chang-Hoon , Lee Jun-Ki , Kim Dong-Soo , Kim Hyong-Joon , Shin Joong-Shik , Lee Hea-Beoum , Choi Byoung-Deog

… We studied the interface state generation and electron trapping by hot electrons under gate-induced drain leakage (GIDL) stress in p-type metal oxide semiconductor field-effect transistors (P-MOSFETs), which are used as the high-voltage core circuit of flash memory devices. … When negative voltage was applied to a drain in the off-state, a GIDL current was generated, but when high voltage was applied to the drain, electrons had a high energy. …

Jpn J Appl Phys 51(11), 111202-111202-5, 2012-11-25

The Japan Society of Applied Physics
4

A Study of Sputtered TiN Gate Electrode Etching with Various Wet Chemicals and Post Etch Annealing for Complementary Metal--Oxide--Semiconductor Device Integration Applications

Heo Seung Chan , Yoo Dongjun , Choi Moon Suk , Kim Dohyung , Chung Chulwon , Choi Changhwan

… Wet chemicals for etching sputtered TiN metal gate and post etch annealing on HfO2 and HfSiON gate dielectrics were studied with metal--oxide--semiconductor devices. … Difference in equivalent oxide thickness (EOT) is negligible among etchants while the lowest leakage current density (J_{\text{g}}) is attained with only SPM solution. …

Jpn J Appl Phys 51(10), 101203-101203-4, 2012-10-25

The Japan Society of Applied Physics
5

Diamond Field-Effect Transistors with 1.3 A/mm Drain Current Density by Al2O3 Passivation Layer

Hirama Kazuyuki , Sato Hisashi , Harada Yuichi , Yamamoto Hideki , Kasu Makoto

… Using nitrogen-dioxide (NO2) adsorption treatment and Al2O3 passivation technique, we improved drain current (I_{\text{DS}}) of hydrogen-terminated (H-terminated) diamond field-effect transistors (FETs). … The Al2O3 passivation layer also serves as a gate-insulator in a gate region. …

Jpn J Appl Phys 51(9), 090112-090112-5, 2012-09-25

The Japan Society of Applied Physics
6

Analytical Simulation of I-V Characteristics for Self-Biased Channel Diode [in Japanese]

SUGAWARA Fumihiko , ENDO Morio , KUDOH Tsugutomo , HOSHI Hideaki , YAMAGUCHI Hideo , OHNUMA Koichi

… An increase ratio of a reverse leakage current of the SBCD for temperature is significantly less than that of the Schottky barrier diode (SBD). … This relative insensitivity of the SBCD reverse current to rising temperature can be explained in terms of the temperature dependence of the parameters composed of the reverse leakage current by the analytical simulation. …

IEEJ Transactions on Electronics, Information and Systems 132(9), 1429-1436, 2012-09-01

J-STAGE CrossRef References (17)
7

Residual Clamping Force and Dynamic Random Access Memory Data Retention Improved by Gate Tungsten Etch Dechucking Condition in a Bipolar Electrostatic Chuck

Lee Chung-Yuan , Lai Chao-Sung , Yang Chia-Ming , Wang David HL , Lin Betty , Lee Siimon , Huang Chi-Hung , Wei Chen Chang

… The residual clamping force and data retention fail bit count (FBC) of DRAM showed strong correlations to the gate tungsten etch dechucking process condition. … Electrical characterization analysis of the FBC proved that the retention loss was mainly due to junction leakage rather than gate-induced-drain-leakage current. …

Jpn J Appl Phys 51(8), 086502-086502-5, 2012-08-25

The Japan Society of Applied Physics
8

Disturbance Characteristics of Vertical Channel Phase Change Random Access Memory Array

Kim Kyung Soo , Cho Il Hwan

… A novel vertical channel phase change random access memory (VPCRAM) was proposed for reducing leakage current and increasing chip density of phase change random access memory (PCRAM). … Electrical disturbance characteristics are determined by both channel potential coupling and junction leakage current between adjacent cells. …

Jpn J Appl Phys 51(8), 084302-084302-5, 2012-08-25

The Japan Society of Applied Physics
9

Experimental Study of Floating-Gate-Type Metal--Oxide--Semiconductor Capacitors with Nanosize Triangular Cross-Sectional Tunnel Areas for Low Operating Voltage Flash Memory Application

Liu Yongxun , Guo Ruofeng , Kamei Takahiro , Matsukawa Takashi , Endo Kazuhiko , O'uchi Shinichi , Tsukada Junichi , Yamauchi Hiromi , Ishikawa Yuki , Hayashida Tetsuro , Sakamoto Kunihiro , Ogura Atsushi , Masahara Meishoku

… The floating-gate (FG)-type metal--oxide--semiconductor (MOS) capacitors with planar (planar-MOS) and three-dimensional (3D) nanosize triangular cross-sectional tunnel areas (3D-MOS) have successfully been fabricated by introducing rapid thermal oxidation (RTO) and postdeposition annealing (PDA), and their electrical characteristics between the control gate (CG) and FG have been systematically compared. …

Jpn J Appl Phys 51(6), 06FF01-06FF01-6, 2012-06-25

The Japan Society of Applied Physics
10

Study on Preparation of High-k Organic--Inorganic Thin Film for Organic--Inorganic Thin Film Transistor Gate Dielectric Application

Lee Wen-Hsi , Liu Chao-Te , Lee Ying-Chieh

… In this study, we describe the spin-coating deposition of a colloidal nanoparticle suspension to obtain an ultra-thin organic--inorganic composite film as a gate insulator for organic thin film transistor (O-TFT) application. …

Jpn J Appl Phys 51(6), 061603-061603-7, 2012-06-25

The Japan Society of Applied Physics
11

Channel Recessed One Transistor Dynamic Random Access Memory with SiO2/Si3N4/SiO2 Gate Dielectric

Park Jin-Kwon , Yang Jong-Heon , Cho Won-Ju

… A fully depleted (FD) single-transistor dynamic random-access memory (1T-DRAM) cell with SiO2--Si3N4--SiO2 (ONO) stacked gate dielectric was fabricated on a recessed silicon channel. … The electrical and memory characteristics of a 1T-DRAM with a stacked ONO gate dielectric were compared with those of 1T-DRAM cell with a single SiO2 gate insulator. …

Jpn J Appl Phys 51(6), 06FE08-06FE08-4, 2012-06-25

The Japan Society of Applied Physics
12

Optimization of Source/Drain Doping Level of Carbon Nanotube Field-Effect Transistors to Suppress OFF-State Leakage Current while Keeping Ideal ON-State Current

Algul Berrin Pinar , Uchida Ken

… The effects of doping concentration variation in source/drain junctions on the characteristics of carbon nanotube field-effect transistors (CNFETs) have been studied in order to realize high performance CNFETs, where suppressed OFF-state leakage current and ideal maximum ON-state current were obtained. …

Jpn J Appl Phys 51(6), 06FD27-06FD27-4, 2012-06-25

The Japan Society of Applied Physics
13

Characteristics of n-Type Asymmetric Schottky-Barrier Transistors with Silicided Schottky-Barrier Source and Heavily n-Type Doped Channel and Drain

Lin Zer-Ming , Lin Horng-Chih , Huang Tiao-Yuan

… By eliminating the SB drain junction contained in conventional symmetrical-type SB metal--oxide--semiconductor field-effect transistors (MOSFETs), a larger on-state current is achievable. … Moreover, combined with the adoption of fully depleted thin-film channel, the off-state leakage current can be efficiently suppressed as well. … A decrease in channel and/or gate oxide thicknesses can contribute to the improvement of the SS of this region. …

Jpn J Appl Phys 51(6), 064301-064301-6, 2012-06-25

The Japan Society of Applied Physics
14

Nanowatt-Power-Level Automatic Switch Combining ED-CMOS Circuit and LED

UTSUNOMIYA Fumiyasu , DOUSEKI Takakuni

… The level converter is a single-input latch-type multi-Vth CMOS circuit featuring the use of an enhancement-mode nMOSFET and a depletion-mode common-gate nMOSFET as a pair of driver transistors. … The ED-CMOS level converter cuts the DC current path; …

IEICE Transactions on Electronics 95(6), 1104-1109, 2012-06-01

J-STAGE CrossRef References (8)
15

Comparison of Two Types of Recessed-Gate Normally-Off AlGaN/GaN Heterostructure Field Effect Transistors

He Zhiyuan , Li Jialin , Wen Yuhua , Shen Zhen , Yao Yao , Yang Fan , Ni Yiqiang , Wu Zhisheng , Zhang Baijun , Liu Yang

… In this report, two types of normally-off AlGaN/GaN heterostructure field effect transistors (HFETs) with recessed-gate structure have been fabricated by using common technique of induced coupled plasma (ICP) dry etching and a novel technique of selective area growth (SAG), respectively. …

Jpn J Appl Phys 51(5), 054103-054103-5, 2012-05-25

The Japan Society of Applied Physics
16

Source/Drain Engineering for High Performance Vertical MOSFET

IMAMOTO Takuya , ENDOH Tetsuo

… In this paper, Source/Drain (S/i>/D) engineering for high performance (HP) Vertical MOSFET (V-MOSFET) in 3Xnm generation and its beyond is investigated, by using gradual S/i>/D profile while degradation of driving current (ION) due to the parasitic series resistance (Rpara) is minimized through two-dimensional device simulation taking into account for gate-induced-drain-leakage (GIDL). …

IEICE Transactions on Electronics 95(5), 807-813, 2012-05-01

J-STAGE CrossRef References (12)
17

Electroluminescence from One-Dimensionally Self-Aligned Si-Based Quantum Dots with High Areal Dot Density

Makihara Katsunori , Deki Hidenori , Ikeda Mitsuhisa , Miyazaki Seiichi

… In semitransparent Au-gate diodes with self-aligned dots so-prepared, when carriers were injected to the self-aligned Si-QDs from the n-Si(100) substrate for electrons and from the Au top electrode for holes, electroluminescence (EL) in the near-infrared region at room temperature becomes observable with an increase in current at positive biases over a threshold voltage as low as {\sim}1.2 V at the Au top electrode. …

Jpn J Appl Phys 51(4), 04DG08-04DG08-5, 2012-04-25

The Japan Society of Applied Physics
18

Recovery Characteristics of Anomalous Stress-Induced Leakage Current of 5.6 nm Oxide Films

Inatsuka Takuya , Kumagai Yuki , Kuroda Rihito , Teramoto Akinobu , Sugawa Shigetoshi , Ohmi Tadahiro

… Anomalous stress-induced leakage current (SILC), which has a much larger current density than average SILC, causes severe bit error in flash memories. … Some of the anomalous cells have random telegraph signals (RTSs) of gate leakage current, which are characterized as discrete and random switching phenomena. …

Jpn J Appl Phys 51(4), 04DC02-04DC02-6, 2012-04-25

The Japan Society of Applied Physics
19

Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays

KOTABE Akira , TAKEMURA Riichiro , YANAGAWA Yoshimitsu , SEKIGUCHI Tomonori , ITOH Kiyoo

… A small-sized leakage-controlled gated sense amplifier (SA) and relevant circuits are proposed for 0.5-V multi-gigabit DRAM arrays. … The gate level control of the high-VT NMOSs and the gate level compensation circuit for PVT variations reduce the leakage current of the proposed SA to 2% of that without the control, and its effectiveness was confirmed using a 50-nm test chip. …

IEICE Transactions on Electronics 95(4), 594-599, 2012-04-01

J-STAGE CrossRef References (7)
20

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme

YOSHIMOTO Shusuke , TERADA Masaharu , OKUMURA Shunsuke , SUZUKI Toshikazu , MIYANO Shinji , KAWAGUCHI Hiroshi , YOSHIMOTO Masahiko

… The floating bitline and the LSBD respectively consist of a precharge-less CMOS equalizer (transmission gate) and an nMOS write-back driver. … In addition, the proposed scheme reduces a leakage current from the write bitline because of the floating write bitline. … The active leakage is reduced by 33% at the FF corner, 125°C. …

IEICE Transactions on Electronics 95(4), 572-578, 2012-04-01

J-STAGE CrossRef References (15)

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