Search Results:　 1-4 of 4

1

A Non-snapback ESD Protection Clamp Circuit Using Isolated Parasitic Capacitance in a 0.35μm Bipolar-CMOS-DMOS Process

PARK Jae-Young , KIM Dae-Woo , SON Young-Sang , SONG Jong-Kyu , JANG Chang-Soo , JUNG Won-Young

… The proposed ESD clamp has a non-snapback characteristic because of gate-coupled effect. … From the measurement, it was observed that the proposed ESD clamp has approximately 40% lower triggering voltage compared to the conventional gate-grounded NMOS ESD clamp. …

IEICE Transactions on Electronics 94(5), 796-801, 2011-05-01

J-STAGE CrossRef References (13)
2

Nanosized-Metal-Grain-Induced Characteristic Fluctuation in 16 nm Complementary Metal--Oxide--Semiconductor Devices and Digital Circuits

Li Yiming

… In this work, we investigate the effect of random work functions (WKs) resulting from the nanosized grains of a metal gate on 16 nm metal--oxide--semiconductor field-effect transistor (MOSFET) devices and circuits. … The random number and position of nanosized metal grains induce rather different random WKs on a MOSFET gate, which cannot be modeled using an averaged WK; …

Jpn J Appl Phys 50(4), 04DC22-04DC22-6, 2011-04-25

The Japan Society of Applied Physics
3

A Non-snapback NMOS ESD Clamp Circuit using Gate-Coupled Scheme with Isolated Well in a Bipolar-CMOS-DMOS Process(Session 7B : Si IC and Circuit Technology)

PARK Jae-Young , KIM Dae-Woo , SON Young-Sang , HA Jong-Chan , SONG Jong-Kyu , JANG Chang-Soo , JUNG Won-Young

… The proposed ESD clamp has a non-snapback characteristics using gate-coupled effect. … From the measurement, it was observed that the proposed ESD clamp has approximately 50% lower triggering voltage compared to the conventional gate-grounded NMOS ESD clamp without degradation of the other ESD design key parameter. …

Technical report of IEICE. SDM 110(110), 269-274, 2010-06-23

CiNii Fulltext PDF - Subscription References (13)
4

A Non-snapback NMOS ESD Clamp Circuit using Gate-Coupled Scheme with Isolated Well in a Bipolar-CMOS-DMOS Process(Session 7B : Si IC and Circuit Technology)

PARK Jae-Young , KIM Dae-Woo , SON Young-Sang , HA Jong-Chan , SONG Jong-Kyu , JANG Chang-Soo , JUNG Won-Young

… The proposed ESD clamp has a non-snapback characteristics using gate-coupled effect. … From the measurement, it was observed that the proposed ESD clamp has approximately 50% lower triggering voltage compared to the conventional gate-grounded NMOS ESD clamp without degradation of the other ESD design key parameter. …

IEICE technical report. Electron devices 110(109), 269-274, 2010-06-23

CiNii Fulltext PDF - Subscription References (13)

Search Results:　 1-4 of 4

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Search Results:　 1-4 of 4