Timing Verification System for Relay Circuit Behaviors.

• FUKUDA Mitsuko

  Power & Industrial System R&D Division, Hitachi, Ltd.

• YAMADA Naoyuki

  Power & Industrial System R&D Division, Hitachi, Ltd.

• TESHIMA Toshiaki

  Omika Works, Hitachi, Ltd.

• KAN Ken'ichi

  Omika Works, Hitachi, Ltd.

• UTSUNOMIYA Mitsugu

  Omika Works, Hitachi, Ltd.

書誌事項

タイトル別名

• Timing Verification System for Relay Ci

抄録

<BR>A timing verification system for analogue relay circuits has been developed. The verification is performed by Time-Symbolic Logic (TSL) simulation that allows symbolic representation of the time. With representation of the relay actuation time by time-variables, TSL simulation can simulate all possible behaviors that differ with the timing of relay action. To reduce the simulation cost, the simulation technique was improved using the characteristics of the relay circuits. Users can verify the circuit behavior without preparing numerous simulation inputs or executing numerous simulation cases. <BR>The developed system was applied to the verification of actual circuits. The circuit behaviors with all the possible timings under the realistic constraints were simulated and verified. These application studies confirmed that the developed system is useful and effective.

収録刊行物

• Ｊｏｕｒｎａｌ　ｏｆ　Ｎｕｃｌｅａｒ　Ｓｃｉｅｎｃｅ　ａｎｄ　Ｔｅｃｈｎｏｌｏｇｙ（日本原子力学会英文論文誌）

  Ｊｏｕｒｎａｌ　ｏｆ　Ｎｕｃｌｅａｒ　Ｓｃｉｅｎｃｅ　ａｎｄ　Ｔｅｃｈｎｏｌｏｇｙ（日本原子力学会英文論文誌） 33 (6), 455-463, 1996

  一般社団法人 日本原子力学会

キーワード

• timing verification system
• analogue relays
• relay circuit
• time-symbolic logic simulation
• timing properties

詳細情報

• CRID: 1390001204093738496
• NII論文ID: 10002074875
• NII書誌ID: AA00703720
• DOI: 10.3327/jnst.33.455
• COI: 1:CAS:528:DyaK28XksVyrurk%3D
• ISSN: 18811248
• ISSN: 00223131
• NDL書誌ID: 4060393
• Web Site: https://ndlsearch.ndl.go.jp/books/R000000004-I4060393
• 本文言語コード: en
• データソース種別:
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