層間バンプ接続法(B^2it^<TM>)配線板の熱特性評価 Thermal Management Estimations for B^2it^<TM>)Printed Wiring Boards with Bump(Filled Via Hole)Interconnection

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抄録

We have developed B<SUP>2</SUP>it<SUP>TM</SUP> (Buried Bump interconnection technology) printed wiring boards (PWB's) for high density and high performance wiring boards or substrates. Ordinary PWB's have low thermal conductivity because of their organic materials, compared with ceramic substrates and so on. The B<SUP>2</SUP>it<SUP>TM</SUP> PWB's have filled via holes by silver paste bumps to connect wiring lines between neighbor layers. The feature is different from ordinary PWB's having copper-plated through holes. This paper reports the thermal management properties for the B<SUP>2</SUP>it<SUP>TM</SUP> PWB's by measuring the thermal resistance of several filled via hole situation. And a thermal conductivity of the via hole material was simulated from the measurement values. As the results, the thermal conductivity of the via hole was very high to compare with that of the normal printed silver paste, and the B<SUP>2</SUP>it<SUP>TM</SUP> PWB's had good thermal management property enough to high density packaging.

収録刊行物

  • 回路実装学会誌  

    回路実装学会誌 13(1), 44-49, 1998-01-20 

    The Japan Institute of Electronics Packaging

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各種コード

  • NII論文ID(NAID)
    10002523122
  • NII書誌ID(NCID)
    AN10564349
  • 本文言語コード
    JPN
  • 資料種別
    ART
  • ISSN
    13410571
  • NDL 記事登録ID
    4380006
  • NDL 雑誌分類
    ZN33(科学技術--電気工学・電気機械工業--電子工学・電気通信)
  • NDL 請求記号
    Z16-1820
  • データ提供元
    CJP書誌  CJP引用  NDL  J-STAGE 
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