Analysis and Compensation of Voltage Distortion by Zero Current Clamping in Voltage-Fed PWM Inverter (「高周波共振形電力変換関連技術」特集号) Analysis and Compensation of Voltage Distortion by Zero Current Clamping in Voltage-Fed PWM Inverter

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In voltage-fed PWM inverter, the relation between the reference voltage and the output voltage is nonlinear. Especially, when the currents are around zero point, the nonlinear voltage distortion invokes the most serious problems in the system performance. In this paper, the analysis of the voltage distortion by the zero current clamping phenomenon is discussed. From this analysis, a novel distortion voltage compensation strategy that eliminates zero current clamping is presented. Experimental results are also presented to demonstrate the validity of the proposed method.

収録刊行物

  • 電気学会論文誌. D, 産業応用部門誌 = The transactions of the Institute of Electrical Engineers of Japan. D, A publication of Industry Applications Society  

    電気学会論文誌. D, 産業応用部門誌 = The transactions of the Institute of Electrical Engineers of Japan. D, A publication of Industry Applications Society 117(2), 160-165, 1997-02 

    The Institute of Electrical Engineers of Japan

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各種コード

  • NII論文ID(NAID)
    10002723845
  • NII書誌ID(NCID)
    AN10012320
  • 本文言語コード
    ENG
  • 資料種別
    ART
  • ISSN
    09136339
  • NDL 記事登録ID
    4128704
  • NDL 雑誌分類
    ZN31(科学技術--電気工学・電気機械工業)
  • NDL 請求記号
    Z16-1608
  • データ提供元
    CJP書誌  NDL  J-STAGE 
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