Analysis and Compensation of Voltage Distortion by Zero Current Clamping in Voltage-Fed PWM Inverter (「高周波共振形電力変換関連技術」特集号) Analysis and Compensation of Voltage Distortion by Zero Current Clamping in Voltage-Fed PWM Inverter
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In voltage-fed PWM inverter, the relation between the reference voltage and the output voltage is nonlinear. Especially, when the currents are around zero point, the nonlinear voltage distortion invokes the most serious problems in the system performance. In this paper, the analysis of the voltage distortion by the zero current clamping phenomenon is discussed. From this analysis, a novel distortion voltage compensation strategy that eliminates zero current clamping is presented. Experimental results are also presented to demonstrate the validity of the proposed method.
- IEEJ Transactions on Sensors and Micromachines
IEEJ Transactions on Sensors and Micromachines 117(2), 160-165, 1997-02
The Institute of Electrical Engineers of Japan