ダイポーラ変調における3レベルインバータの出力電圧高調波解析 [in Japanese] Analysis of Output Voltage of Three-level Inverter Using Dipola Modulation [in Japanese]
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Recently, a neutral point-clamped type inverter (three-level inverter) with large capacity has come to be used in a train, etc. for driving A. C. motor. The three-level inverter has an advantage of being low in harmonics unlike conventional two-level inverter. Moreover, if DC-voltage is at same voltage, a transistor or an IGBT whose switching frequency is high can be used as a substitute for high-voltage GTO thyristor, because the number of switching elements in one arm is double.<br>However, the three-level inverter has a drawback in that the output voltage is not controllable smoothly in the case of output voltage being low. It is because the switching element needs a minimum on-off time; this is especially remarkable with the GTO thyristor whose minimum on-off time is long. In order to avoid operation with this drawback, the three-level inverter frequently adopts a dipola modulation. The dipola modulation adds a bias component to the control signal of output voltage lest the control signal should become low-level, and it generates simultaneously a pulse voltage to cancel the bias component.<br>In this paper, first, the output voltage of a three-level inverter with single phase using dipola modulation is analyzed, then its characteristics of harmonics are made clear. Second, in the case of a three-level inverter with three phases, zero-phase sequence component of harmonics are described. Third, characteristics of harmonics are analyzed in the case of three-level inverter being multiply. Lastly, what are described above are verified by simulation.
- IEEJ Transactions on Sensors and Micromachines
IEEJ Transactions on Sensors and Micromachines 117(5), 637-644, 1997-05
The Institute of Electrical Engineers of Japan