Switched Current Circuit using Fixed Gate-Potential Transistor and Automatic Tuning Circuit
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- Ishii Hirotomo
- Tokyo Institute of Technology
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- Takagi Shigetaka
- Tokyo Institute of Technology
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- Fujii Nobuo
- Tokyo Institute of Technology
Bibliographic Information
- Other Title
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- ゲート電位を固定したトランジスタを用いたスイッチトカレント回路とその自動調整回路
- ゲート デンイ オ コテイシタ トランジスタ オ モチイタ スイッチト カレン
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Abstract
Clock feedthrough (CFT) error is one of the most important problems for switched current (SI) circuits. This paper proposes a SI circuit which can reduce CFT error drastically. The proposed circuit will theoretically reduce both signal-dependent and independent errors by using CMOS switches under a fixed and appropriate bias. Although conventional circuits based on a similar idea need operational amplifiers or additional capacitors, the circuit proposed in this paper requires only MOSFETs. The proposed circuit can reduce clock feedthrough current with less power consumption and chip area compared to those of conventional circuits. An automatic tuning circuit, which controls the gate potential appropriately, is also proposed. Simulation results demonstrate the effectiveness of the proposed circuits.
Journal
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- IEEJ Transactions on Electronics, Information and Systems
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IEEJ Transactions on Electronics, Information and Systems 117 (8), 1035-1042, 1997
The Institute of Electrical Engineers of Japan
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Keywords
Details 詳細情報について
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- CRID
- 1390001204608110464
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- NII Article ID
- 130006843876
- 10002810999
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- NII Book ID
- AN10065950
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- ISSN
- 13488155
- 03854221
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- NDL BIB ID
- 4266969
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- Data Source
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- JaLC
- NDL
- Crossref
- CiNii Articles
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- Abstract License Flag
- Disallowed