A Neural Network Parallel Algorithm for One-Dimensional Gate Assignment Problems

• Tsuchiya Kazuhiro

  FUJIFACOM CORPORATION

• Takefuji Yoshiyasu

  Keio University

• Kurotani Ken-ichi

  FUJIFACOM CORPORATION

Bibliographic Information

Other Title

• ニューラルネットワークによる一次元ゲート割り当て問題の解法
• ニューラル ネットワーク ニヨル 1ジゲン ゲート ワリアテ モンダイ ノ

Abstract

A near-optimum parallel algorithm for solving the one-dimensional gate assignment problem is presented in this paper where the problem is NP-hard and one of the most fundamental layout problems in VLSI design. The proposed system is composed of n x n processing elements based on the artificial two-dimensional maximum neural network for (n+2)-gate assignment problems. Our algorithm has discovered the improved solutions in the benchmark problems over the best existing algorithms. The proposed approach is applicable to other VLSI layout problems such as the PLA (Programable Logic Array) folding problem.

Journal

• IEEJ Transactions on Electronics, Information and Systems

  IEEJ Transactions on Electronics, Information and Systems 117 (10), 1479-1484, 1997

  The Institute of Electrical Engineers of Japan

Keywords

• ニューラルネットワーク
• 一次元ゲート割り当て問題
• パラレルアルゴリズム
• ワインバーガーアレイ
• PLA folding問題

Details

• CRID: 1390282679584370176
• NII Article ID: 130006843582
• NII Article ID: 10002811900
• NII Book ID: AN10065950
• DOI: 10.1541/ieejeiss1987.117.10_1479
• ISSN: 13488155
• ISSN: 03854221
• NDL BIB ID: 4303599
• Web Site: https://ndlsearch.ndl.go.jp/books/R000000004-I4303599
• Web Site: https://www.jstage.jst.go.jp/article/ieejeiss1987/117/10/117_10_1479/_pdf
• Data Source:
  • JaLC
  • NDL
  • Crossref
  • CiNii Articles
• Abstract License Flag: Disallowed