Fast Parallel Multiplier using 2×2 Submultipliers

• Lee Sang-Gu

  Hannam Univ.

• Akizuki Kageo

  Waseda Univ.

Bibliographic Information

Other Title

• 2×2部分乗算器を用いた高速並列乗算器の構成
• 2 2 ブブン ジョウザンキ オ モチイタ コウソク ヘイレツ ジョウザンキ ノ コウセイ
• Fast Parallel Multiplier using 2×2 Submultipliers

Abstract

In this paper, we propose a novel parallel multiplication scheme using 2×2 submultipliers. It adopts a new encoding method which halves the number of partical products through 2×2 submultipliers and rearrangement of primitive partical products. We present the parallel multiplication algorithm and design a 16bit×16bit multiplier architecture of the proposed method, which is suitable for VLSI implementation. The proposed scheme can be easily extended to large-size multipliers with 32, 54 or even longer bits. This parallel mltiplication scheme can be applied to many areas such as DSP, MPEG and so on.

Journal

• IEEJ Transactions on Electronics, Information and Systems

  IEEJ Transactions on Electronics, Information and Systems 119 (1), 136-142, 1999

  The Institute of Electrical Engineers of Japan

Keywords

• parallel multiplication
• 2×2 submultiplier
• partial product

Details

• CRID: 1390282679585083648
• NII Article ID: 130006844135
• NII Article ID: 10002816064
• NII Book ID: AN10065950
• DOI: 10.1541/ieejeiss1987.119.1_136
• ISSN: 13488155
• ISSN: 03854221
• NDL BIB ID: 971498
• Web Site: https://ndlsearch.ndl.go.jp/books/R000000004-I971498
• Web Site: https://www.jstage.jst.go.jp/article/ieejeiss1987/119/1/119_1_136/_pdf
• Data Source:
  • JaLC
  • NDL
  • Crossref
  • CiNii Articles
• Abstract License Flag: Disallowed