VLSI Architecture for FIR Filter with Very High Throughput Keeping Small Latency

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  • 高スループット形FIRフィルタの滞在時間最小化VLSIアーキテクチャ
  • コウスループットガタ FIR フィルタ ノ タイザイ ジカン サイショウカ VLSI アーキテクチャ

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Abstract

This paper presents VLSI architecture for FIR filter with very high throughput keeping small latency. In this architecture, a block implementation with characteristic of multirate system is applied, so that very high sampling rate becomes possible while processing speed of PE's is held constant. Moreover, by using distributed arithmetic, of which processing time depends on only word length and data of input and output are given serially, latency can be minimized and number of signal pins can be reduced to 2L for block length L. Next, we reveal a new method of lower power dissipation, by considering not only the properties of function Φ but also impulse response of even symmetry and odd symmetry. As a result we show that a 32-tap FIR digital filter can be realized with very high sampling rate of 95.2MHz and the small latency of 315ns, by using 0.6μm CMOS technology. In this case, the processor is implemented with relatively low power of 5.41 W.

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