Easily Manufacturable Shallow Trench Isolation for Gigabit Dynamic Random Access Memory

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著者

    • Roh Byung Hyug Roh Byung
    • Technology Development, Memory Device Business, Samsung Electronicss Co., San #24, Nongseo-lee, Kiheung-eup, Yongin-gun, Kyungki-do, Korea
    • Cho Yun Hee Cho Yun
    • Technology Development, Memory Device Business, Samsung Electronicss Co., San #24, Nongseo-lee, Kiheung-eup, Yongin-gun, Kyungki-do, Korea
    • Shin Yu Gyun [他] Shin Yu
    • Technology Development, Memory Device Business, Samsung Electronicss Co., San #24, Nongseo-lee, Kiheung-eup, Yongin-gun, Kyungki-do, Korea
    • Hong Chang
    • Technology Development, Memory Device Business, Samsung Electronicss Co., San #24, Nongseo-lee, Kiheung-eup, Yongin-gun, Kyungki-do, Korea
    • Gwun Sang
    • Technology Development, Memory Device Business, Samsung Electronicss Co., San #24, Nongseo-lee, Kiheung-eup, Yongin-gun, Kyungki-do, Korea
    • Lee Kang
    • Technology Development, Memory Device Business, Samsung Electronicss Co., San #24, Nongseo-lee, Kiheung-eup, Yongin-gun, Kyungki-do, Korea
    • Kang Ho
    • Technology Development, Memory Device Business, Samsung Electronicss Co., San #24, Nongseo-lee, Kiheung-eup, Yongin-gun, Kyungki-do, Korea
    • Kim Ki
    • Technology Development, Memory Device Business, Samsung Electronicss Co., San #24, Nongseo-lee, Kiheung-eup, Yongin-gun, Kyungki-do, Korea
    • Park Jong
    • Technology Development, Memory Device Business, Samsung Electronicss Co., San #24, Nongseo-lee, Kiheung-eup, Yongin-gun, Kyungki-do, Korea

抄録

A simple and easily manufacturable shallow trench isolation (STI) process is developed for 1 Gbit dynamic random access memory (DRAM) and possibly DRAMs with ever greater capacity. The main features of this STI scheme are dual slope trench formation and selective dry-etching-assisted chemical mechanical polishing (CMP) planarization. The dual slope trench is formed by utilizing polymer generation during trench etching to improve the sub-threshold conduction characteristics (hump-free sub-threshold) and reduce the threshold voltage variation. The basic elements of dry-etching-assisted planarization are to locally form oxide mesas using a highly selective dry etching, and to minimize the amount of CMP simply by removing the locally formed oxide mesas. This new dry-etching-assisted CMP planarization significantly reduces dishing in the large field area and improves the flatness between the high and low pattern density areas such as the cell array and periphery region in a high-density DRAM.

収録刊行物

  • Japanese journal of applied physics. Pt. 1, Regular papers & short notes  

    Japanese journal of applied physics. Pt. 1, Regular papers & short notes 35(9A), 4618-4623, 1996-09-15 

    Publication Office, Japanese Journal of Applied Physics, Faculty of Science, University of Tokyo

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各種コード

  • NII論文ID(NAID)
    10004612885
  • NII書誌ID(NCID)
    AA10457675
  • 本文言語コード
    EN
  • 資料種別
    ART
  • 雑誌種別
    大学紀要
  • ISSN
    0021-4922
  • NDL 記事登録ID
    4060131
  • NDL 雑誌分類
    ZM35(科学技術--物理学)
  • NDL 請求記号
    Z53-A375
  • データ提供元
    CJP書誌  NDL  JSAP 
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