Easily Manufacturable Shallow Trench Isolation for Gigabit Dynamic Random Access Memory.

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  • Roh Byung Hyug
    Technology Development, Memory Device Business, Samsung Electronicss Co., San #24, Nongseo–lee, Kiheung–eup, Yongin–gun, Kyungki–do, Korea
  • Cho Yun Hee
    Technology Development, Memory Device Business, Samsung Electronicss Co., San #24, Nongseo–lee, Kiheung–eup, Yongin–gun, Kyungki–do, Korea
  • Shin Yu Gyun
    Technology Development, Memory Device Business, Samsung Electronicss Co., San #24, Nongseo–lee, Kiheung–eup, Yongin–gun, Kyungki–do, Korea
  • Hong Chang Gi
    Technology Development, Memory Device Business, Samsung Electronicss Co., San #24, Nongseo–lee, Kiheung–eup, Yongin–gun, Kyungki–do, Korea
  • Gwun Sang Dong
    Technology Development, Memory Device Business, Samsung Electronicss Co., San #24, Nongseo–lee, Kiheung–eup, Yongin–gun, Kyungki–do, Korea
  • Lee Kang Yun
    Technology Development, Memory Device Business, Samsung Electronicss Co., San #24, Nongseo–lee, Kiheung–eup, Yongin–gun, Kyungki–do, Korea
  • Kang Ho Gyu
    Technology Development, Memory Device Business, Samsung Electronicss Co., San #24, Nongseo–lee, Kiheung–eup, Yongin–gun, Kyungki–do, Korea
  • Kim Ki Nam
    Technology Development, Memory Device Business, Samsung Electronicss Co., San #24, Nongseo–lee, Kiheung–eup, Yongin–gun, Kyungki–do, Korea
  • Park Jong Woo
    Technology Development, Memory Device Business, Samsung Electronicss Co., San #24, Nongseo–lee, Kiheung–eup, Yongin–gun, Kyungki–do, Korea

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  • Easily Manufacturable Shallow Trench Is

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Abstract

A simple and easily manufacturable shallow trench isolation (STI) process is developed for 1 Gbit dynamic random access memory (DRAM) and possibly DRAMs with ever greater capacity. The main features of this STI scheme are dual slope trench formation and selective dry-etching-assisted chemical mechanical polishing (CMP) planarization. The dual slope trench is formed by utilizing polymer generation during trench etching to improve the sub-threshold conduction characteristics (hump-free sub-threshold) and reduce the threshold voltage variation. The basic elements of dry-etching-assisted planarization are to locally form oxide mesas using a highly selective dry etching, and to minimize the amount of CMP simply by removing the locally formed oxide mesas. This new dry-etching-assisted CMP planarization significantly reduces dishing in the large field area and improves the flatness between the high and low pattern density areas such as the cell array and periphery region in a high-density DRAM.

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