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- 松本 佳宣
- 豊橋技術科学大学
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- 松浦 みほ
- 豊橋技術科学大学
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- Dharmasena G. R.
- Toyohashi University of Technology
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- 石田 誠
- 豊橋技術科学大学
書誌事項
- タイトル別名
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- Development of sensitivity and offset calibratable capacitance detection CMOS IC using PLL configuration
- カンド ト オフセット ホショウ カノウ ナ PLL ホウシキ ヨウリョウ ケ
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抄録
A CMOS capacitance detection integrated circuit for silicon capacitive sensors has been developed using PLL configuration. The circuit is composed of two voltage controlled capacitance to frequency converters, a phase sensitive detector, a charge pump and a low pass filter. The circuit has differential configuration in order to supress the circuit power suply dependence and temperature dependence. The circuit is also desiged to be able to calibrate variations of the sensor sensitivity and offset with feedback principle. The circuit was designed with SPICE simulator and fabricated with standared CMOS technology of Toyohashi University of Technology. From the measurment result, the sensitivity and offset can be calibrated with applied bias voltage, and the power supply dependence and temperature dependence of the circuit were neally zero, The circuit is considerd as candidate of detection circuit for surface micromaching capacitve sensors.
収録刊行物
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- 電気学会論文誌E(センサ・マイクロマシン部門誌)
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電気学会論文誌E(センサ・マイクロマシン部門誌) 117 (11), 571-575, 1997
一般社団法人 電気学会
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詳細情報 詳細情報について
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- CRID
- 1390001204461692800
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- NII論文ID
- 10004832774
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- NII書誌ID
- AN1052634X
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- ISSN
- 13475525
- 13418939
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- NDL書誌ID
- 4323371
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- データソース種別
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- JaLC
- NDL
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