感度とオフセット補償可能なPLL方式容量検出CMOSICの試作 Development of sensitivity and offset calibratable capacitance detection CMOSIC

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A CMOS capacitance detection integrated circuit for silicon capacitive sensors has been developed using PLL configuration. The circuit is composed of two voltage controlled capacitance to frequency converters, a phase sensitive detector, a charge pump and a low pass filter. The circuit has differential configuration in order to supress the circuit power suply dependence and temperature dependence. The circuit is also desiged to be able to calibrate variations of the sensor sensitivity and offset with feedback principle. The circuit was designed with SPICE simulator and fabricated with standared CMOS technology of Toyohashi University of Technology. From the measurment result, the sensitivity and offset can be calibrated with applied bias voltage, and the power supply dependence and temperature dependence of the circuit were neally zero, The circuit is considerd as candidate of detection circuit for surface micromaching capacitve sensors.

収録刊行物

  • 電気学会論文誌. E, センサ・マイクロマシン準部門誌 = The transactions of the Institute of Electrical Engineers of Japan. A publication of Sensors and Micromachines Society  

    電気学会論文誌. E, センサ・マイクロマシン準部門誌 = The transactions of the Institute of Electrical Engineers of Japan. A publication of Sensors and Micromachines Society 117(11), 571-575, 1997-11 

    The Institute of Electrical Engineers of Japan

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各種コード

  • NII論文ID(NAID)
    10004832774
  • NII書誌ID(NCID)
    AN1052634X
  • 本文言語コード
    JPN
  • 資料種別
    ART
  • ISSN
    13418939
  • NDL 記事登録ID
    4323371
  • NDL 雑誌分類
    ZN31(科学技術--電気工学・電気機械工業)
  • NDL 請求記号
    Z16-B380
  • データ提供元
    CJP書誌  NDL  J-STAGE 
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