Hardware Petri Nets on Programmable Devices

• Nakamura Morikazu

  University of the Ryukyus

• Amau Yoshiaki

  NTT West

• Matsumura Takashi

  University of the Ryukyus

• Shimabukuro Katsuhiko

  University of the Ryukyus

• Nagayama Itaru

  University of the Ryukyus

• Yamashiro Tsuyoshi

  University of the Ryukyus

Bibliographic Information

Other Title

• プログラマブルデバイスによるハードウェアペトリネット
• プログラマブルデバイス ニ ヨル ハードウェアペトリネット

Abstract

Petri nets are a mathematical tool well suited for modeling and analysis of Discrete Event Dynamic Systems (DEDS). In this paper, we propose and implement hardware Petri nets on programmable devices. The hardware Petri Nets are generated by firstly modeling the target system with a GUI tool, secondly converting the net description into VHDL codes and finally implementing onto FPGA devices. The hardware Petri nets are useful for discrete event simulation in which they can represent perfectly the natural parallelism of the target system in the circuit level. Moreover, our proposed system is regarded as logic circuit development systems in which we can design desired logic circuits by using Petri nets and implement it directly on FPGA as logic circuits.

Journal

• IEEJ Transactions on Electronics, Information and Systems

  IEEJ Transactions on Electronics, Information and Systems 122 (7), 1202-1208, 2002

  The Institute of Electrical Engineers of Japan

Keywords

• Petri net
• Programmable Device
• Discrete Event Simulation
• Logic Controller
• FPGA

Details

• CRID: 1390001204609851776
• NII Article ID: 130006845139
• NII Article ID: 10008844458
• NII Book ID: AN10065950
• DOI: 10.1541/ieejeiss1987.122.7_1202
• ISSN: 13488155
• ISSN: 03854221
• NDL BIB ID: 6204783
• Web Site: https://ndlsearch.ndl.go.jp/books/R000000004-I6204783
• Web Site: https://www.jstage.jst.go.jp/article/ieejeiss1987/122/7/122_7_1202/_pdf
• Data Source:
  • JaLC
  • NDL
  • Crossref
  • CiNii Articles
• Abstract License Flag: Disallowed