Partial Order Reduction for Timed Circuit Verification Based on Level Oriented Model

この論文をさがす

著者

    • KITAI Tomoya
    • Graduate School of Information Science and Engineering, Dept. of Computer Science, Tokyo Institute of Technology
    • OGURO Yusuke
    • Graduate School of Information Science and Engineering, Dept. of Computer Science, Tokyo Institute of Technology
    • YONEDA Tomohiro
    • Infrastructure Systems Research Division, National Institute of Informatics
    • MYERS Chris
    • Department of Electrical and Computer Engineering, University of Utah

収録刊行物

  • IEICE transactions on information and systems

    IEICE transactions on information and systems 86(12), 2601-2611, 2003-12-01

参考文献:  17件中 1-17件 を表示

各種コード

  • NII論文ID(NAID)
    10012560062
  • NII書誌ID(NCID)
    AA10826272
  • 本文言語コード
    ENG
  • 資料種別
    ART
  • ISSN
    09168532
  • データ提供元
    CJP書誌 
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