Zero-Crosstalk Bus Line Structure for Global Interconnects in Si Ultra Large Scale Integration
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In this paper, we propose a novel technique for achieving high-density, high-speed and low-power on-chip bus lines using differential transmission lines. The feasibility of this technique is discussed with a two-dimensional electromagnetic simulator (Ansoft 2D Extractor) and time-domain measurements. Results show that the proposed bus line can transmit at over 12 Gbps. The proposed bus line can reduce wiring area by 30% compared with a conventional co-planar line.
- Jpn J Appl Phys
Jpn J Appl Phys 45(6A), 4977-4981, 2006-06-15
INSTITUTE OF PURE AND APPLIED PHYSICS