Zero-Crosstalk Bus Line Structure for Global Interconnects in Si Ultra Large Scale Integration

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著者

    • Kimura Makoto Kimura Makoto
    • Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan
    • Ito Hiroyuki Ito Hiroyuki
    • Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan
    • Okada Kenichi
    • Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan
    • Masu Kazuya
    • Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan

抄録

In this paper, we propose a novel technique for achieving high-density, high-speed and low-power on-chip bus lines using differential transmission lines. The feasibility of this technique is discussed with a two-dimensional electromagnetic simulator (Ansoft 2D Extractor) and time-domain measurements. Results show that the proposed bus line can transmit at over 12 Gbps. The proposed bus line can reduce wiring area by 30% compared with a conventional co-planar line.

収録刊行物

  • Japanese journal of applied physics. Pt. 1, Regular papers & short notes  

    Japanese journal of applied physics. Pt. 1, Regular papers & short notes 45(6A), 4977-4981, 2006-06-15 

    Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physics

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各種コード

  • NII論文ID(NAID)
    10018148378
  • NII書誌ID(NCID)
    AA10457675
  • 本文言語コード
    EN
  • 資料種別
    ART
  • 雑誌種別
    大学紀要
  • ISSN
    0021-4922
  • NDL 記事登録ID
    7940756
  • NDL 雑誌分類
    ZM35(科学技術--物理学)
  • NDL 請求記号
    Z53-A375
  • データ提供元
    CJP書誌  NDL  JSAP 
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