# Fringing Electric Field Effect on 65-nm-Node Fully Depleted Silicon-on-Insulator Devices

## Abstract

In this study, the fringing electric field effect on 65-nm-node technology fully depleted silicon-on-insulator (FD SOI) device is comprehensively examined. A new anomalous degradation in device on-state/off-state characteristics on a nanoscale metal–oxide–semiconductor field-effect transistor (MOSFET) with high-$\kappa$ gate dielectrics is reported, the so-called fringing-induced barrier lowering (FIBL). This is due to the decrease in fringing electric field and increase in the gate dielectric thickness when gate dielectric permittivity increased. We observe that FIBL can be effectively suppressed using a stack gate dielectric structure. In addition, we also implement a high-$\kappa$ offset spacer to further improve the on-state driving current $I_{\text{on}}$ to approximately 26% higher than that of a conventional silicon dioxide offset spacer and reduce the off-state leakage current $I_{\text{off}}$ by about 34%. This benefit is due to the enhanced high vertical channel electric field obtained via the offset spacer using a high-$\kappa$ material as a spacer. This enhanced fringing electric field can markedly increase $I_{\text{on}}/I_{\text{off}}$ current ratio and reduce subthreshold swing ($S$-factor) to improve MOSFET performance, which implies that gate-to-channel controllability can be improved markedly. This would play an important role beyond the 65-nm-node technology.

## Journal

• Jpn J Appl Phys

Jpn J Appl Phys 45(9A), 6854-6859, 2006-09-15

INSTITUTE OF PURE AND APPLIED PHYSICS

## References:  22

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## Codes

• NII Article ID (NAID)
10018245382
• NII NACSIS-CAT ID (NCID)
AA10457675
• Text Lang
EN
• Article Type
ART
• Journal Type
大学紀要
• ISSN
0021-4922
• NDL Article ID
8055366
• NDL Source Classification
ZM35(科学技術--物理学)
• NDL Call No.
Z53-A375
• Data Source
CJP  NDL  JSAP

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