Retention Mechanism of Localized Silicon–Oxide–Nitride–Oxide–Silicon Embedded NOR Device

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著者

    • Hyun JaeWoong Hyun JaeWoong
    • Semiconductor Device and Material Laboratory, Samsung Advanced Institute of Technology (SAIT), Mt 14-1, Nongseo-ri, Kihung-up, Yongin, Kyungki-do 449-712, Korea
    • Jeong YounSeok Jeong YounSeok
    • Semiconductor Device and Material Laboratory, Samsung Advanced Institute of Technology (SAIT), Mt 14-1, Nongseo-ri, Kihung-up, Yongin, Kyungki-do 449-712, Korea
    • Chae HeeSoon [他] Chae HeeSoon
    • Semiconductor Device and Material Laboratory, Samsung Advanced Institute of Technology (SAIT), Mt 14-1, Nongseo-ri, Kihung-up, Yongin, Kyungki-do 449-712, Korea
    • Seo Sunae
    • Semiconductor Device and Material Laboratory, Samsung Advanced Institute of Technology (SAIT), Mt 14-1, Nongseo-ri, Kihung-up, Yongin, Kyungki-do 449-712, Korea
    • Kim JinHee
    • System LSI Division, Semiconductor Business, Samsung Electronics Co., Ltd., Korea
    • Um MyungYoon
    • System LSI Division, Semiconductor Business, Samsung Electronics Co., Ltd., Korea
    • Lee ByoungJin
    • System LSI Division, Semiconductor Business, Samsung Electronics Co., Ltd., Korea
    • Kim KiChul
    • System LSI Division, Semiconductor Business, Samsung Electronics Co., Ltd., Korea
    • Cho InWook
    • System LSI Division, Semiconductor Business, Samsung Electronics Co., Ltd., Korea
    • Bae GeumJong
    • System LSI Division, Semiconductor Business, Samsung Electronics Co., Ltd., Korea
    • Lee NaeIn
    • System LSI Division, Semiconductor Business, Samsung Electronics Co., Ltd., Korea
    • Kim ChungWoo
    • Semiconductor Device and Material Laboratory, Samsung Advanced Institute of Technology (SAIT), Mt 14-1, Nongseo-ri, Kihung-up, Yongin, Kyungki-do 449-712, Korea

抄録

Reliability studies of localized oxide–nitride–oxide memory (LONOM) devices are presented. The observed reduction in channel threshold voltage as a result of the retention charge loss of a programmed cell is demonstrated in terms of vertical leakage paths. Despite the apparent controversy of charge transport with nitride read-only memory (NROM) devices, the vertical paths are evidently observed via the channel and junction threshold voltage changes, which were monitored using $I_{\text{ds}}$–$V_{\text{ds}}$ curves and gate-induced drain leakage (GIDL) measurements, visualizing the internal status of interface charges and stored charges in a nitride layer.

収録刊行物

  • Japanese journal of applied physics. Pt. 2, Letters  

    Japanese journal of applied physics. Pt. 2, Letters 45(37), L998-L1000, 2006-10-25 

    Japan Society of Applied Physics

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各種コード

  • NII論文ID(NAID)
    10018340497
  • NII書誌ID(NCID)
    AA10650595
  • 本文言語コード
    EN
  • 資料種別
    SHO
  • ISSN
    0021-4922
  • NDL 記事登録ID
    8519669
  • NDL 雑誌分類
    ZM35(科学技術--物理学)
  • NDL 請求記号
    Z54-J337
  • データ提供元
    CJP書誌  NDL  JSAP 
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