Flash Memory Device with 'I' Shape Floating Gate for Sub-70 nm NAND Flash Memory

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著者

    • Jung Sang-Goo Jung Sang-Goo
    • School of Electrical Engineering and Computer Science, Kyungpook National University, Sankyuk-Dong, Buk-Gu, Daegu 702-701, Korea
    • Lee Jong-Ho Lee Jong-Ho
    • School of Electrical Engineering and Computer Science, Kyungpook National University, Sankyuk-Dong, Buk-Gu, Daegu 702-701, Korea

抄録

In this article, we proposed a novel 'I' shape floating gate applicable to the sub-70 nm flash memory cell with high performance and scalability. It has modified floating gate of conventional flash memory to have high coupling-ratio ($\mathit{CR}$), low effect of interference or cross-talk. Specifically, it has ${\sim}13$% higher $\mathit{CR}$ and ${\sim}33/46$% lower effect of cross-talk of the bit-line/word-line state than those of conventional flash memory cell with scale-downed geometry. In addition, 'I' shape flash memory cell shows improved characteristics about programming time, drain disturbance, read current, sub-threshold swing, and drain induced barrier lowering than conventional flash memory cell.

収録刊行物

  • Japanese journal of applied physics. Pt. 2, Letters  

    Japanese journal of applied physics. Pt. 2, Letters 45(45), L1200-L1202, 2006-11-25 

    Japan Society of Applied Physics

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各種コード

  • NII論文ID(NAID)
    10018632537
  • NII書誌ID(NCID)
    AA10650595
  • 本文言語コード
    EN
  • 資料種別
    SHO
  • ISSN
    0021-4922
  • NDL 記事登録ID
    8548595
  • NDL 雑誌分類
    ZM35(科学技術--物理学)
  • NDL 請求記号
    Z54-J337
  • データ提供元
    CJP書誌  NDL  JSAP 
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