暗号回路への電力差分解析攻撃に対するアルゴリズムレベルでの耐性評価

• 佐々木 明彦

  電気通信大学情報工学専攻

• 阿部 公輝

  電気通信大学情報工学専攻

書誌事項

タイトル別名

• Algorithm Level Evaluation of DPA Resistivity against Cryptosystems
• アンゴウ カイロ エ ノ デンリョク サブン カイセキ コウゲキ ニ タイスル アルゴリズム レベル デ ノ タイセイ ヒョウカ

抄録

Paul Kocher has proposed a cryptanalysis technique called Differential Power Analysis (DPA), in which attackers derive secret information such as private keys from a statistical analysis of the power consumption by the target device. There is now a demand to evaluate the DPA resistivity of cryptographic device before the device is actually created. In this paper, we focus on simulating DPA with high speed at algorithm level in upstream of the design process. Messerges used Power Leakage Model to obtain power consumption from Hamming Weight for proof of high-order DPA. However, the correctness of the model has not been verified. In this paper, we verify that difference of power consumption in DPA can be obtained from Power Leakage Model by investigating the cause of power consumption of CMOS circuits and transition probability of logic gates. The verification is performed by means of a circuit simulator. Next we describe a method of performing algorithm level simulation which calculates power consumption using Power Leakage Model. We illustrate the effectiveness of the method by applying it to DPA resistivity evaluation of DES implementation.

収録刊行物

• 電気学会論文誌Ｃ（電子・情報・システム部門誌）

  電気学会論文誌Ｃ（電子・情報・システム部門誌） 126 (10), 1221-1228, 2006

  一般社団法人 電気学会

キーワード

• 電力差分解析
• Power Leakage Model
• ハミングウェイト
• シミュレーション

詳細情報

• CRID: 1390001204605852800
• NII論文ID: 10018780677
• NII書誌ID: AN10065950
• DOI: 10.1541/ieejeiss.126.1221
• ISSN: 13488155
• ISSN: 03854221
• NDL書誌ID: 8526250
• Web Site: https://ndlsearch.ndl.go.jp/books/R000000004-I8526250
• Web Site: http://www.jstage.jst.go.jp/article/ieejeiss/126/10/126_10_1221/_pdf
• 本文言語コード: ja
• データソース種別:
  • JaLC
  • NDL
  • Crossref
  • CiNii Articles
  • KAKEN
• 抄録ライセンスフラグ: 使用不可