A CMOS Multiplier with Large Input Range Using Bias-offset Technique

1 Citations 3 References
  • NAKAMURA Kei
    Faculty of Science and Technology, Tokyo University of Science
  • HYOGO Akira
    Faculty of Science and Technology, Tokyo University of Science
  • SEKINE Keitaro
    Faculty of Science and Technology, Tokyo University of Science

Bibliographic Information

Other Title
  • バイアスオフセット回路技術を用いた広い入力範囲を持つ2段積みCMOS乗算器

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Journal

  • ECT

    ECT 2001 (69), 77-81, 2001-10-19

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Keywords

Details 詳細情報について

  • CRID
    1572261550259704704
  • NII Article ID
    10018971095
  • NII Book ID
    AN10441815
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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