Static Noise Margin Enhancement by Flex-Pass-Gate SRAM

• O'uchi Shin-ichi

  Nanoelectronices Research Institute, National Institute of Advanced Industrial Science and Technology (AIST)

• Masahara Meishoku

  Nanoelectronices Research Institute, National Institute of Advanced Industrial Science and Technology (AIST) Ministry of Economy, Trade and Industry

• Sakamoto Kunihiro

  Nanoelectronices Research Institute, National Institute of Advanced Industrial Science and Technology (AIST)

• Endo Kazuhiko

  Nanoelectronices Research Institute, National Institute of Advanced Industrial Science and Technology (AIST)

• Liu Yungxun

  Nanoelectronices Research Institute, National Institute of Advanced Industrial Science and Technology (AIST)

• Matsukawa Takashi

  Nanoelectronices Research Institute, National Institute of Advanced Industrial Science and Technology (AIST)

• Sekigawa Toshihiro

  Nanoelectronices Research Institute, National Institute of Advanced Industrial Science and Technology (AIST)

• Koike Hanpei

  Nanoelectronices Research Institute, National Institute of Advanced Industrial Science and Technology (AIST)

• Suzuki Eiichi

  Nanoelectronices Research Institute, National Institute of Advanced Industrial Science and Technology (AIST)

Bibliographic Information

Other Title

• フレックス・パスゲートＳＲＡＭによる雑音余裕向上
• フレックス パス ゲート SRAM ニ ヨル ザツオン ヨユウ コウジョウ

Abstract

A Flex-Pass-Gate SRAM, i.e. a fin-type-field-effect-transistor- (FinFET-) based SRAM, is proposed to enhance noise margin during both read and write operations. In its cell, the flip-flop is composed of usual three-terminal- (3T-) FinFETs while pass gates are composed of four-terminal- (4T-) FinFETs. The 4T-FinFETs enable to adopt a dynamic threshold-voltage control in the pass gates. During a write operation, the threshold voltage of the pass gates is lowered to enhance the writing speed and stability. During the read operation, on the other hand, the threshold voltage is raised to enhance the static noise margin. An asymmetric-oxide 4T-FinFET is helpful to manage the leakage current through the pass gate. In this paper, a design strategy of the pass gate with an asymmetric gate oxide is considered, and a TCAD-based Monte Carlo simulation reveals that the Flex-Pass-Gate SRAM based on that design strategy is expected to be effective in half-pitch 32-nm technology for low-standby-power (LSTP) applications, even taking into account the variability in the device performance.

Journal

• IEEJ Transactions on Electronics, Information and Systems

  IEEJ Transactions on Electronics, Information and Systems 128 (6), 919-925, 2008

  The Institute of Electrical Engineers of Japan

Keywords

• SRAM
• static noise margin
• pass gate
• FinFET
• four-terminal FinFET
• asymmetric-oxide four-terminal FinFET

Details

• CRID: 1390282679582739072
• NII Article ID: 10021132699
• NII Book ID: AN10065950
• DOI: 10.1541/ieejeiss.128.919
• ISSN: 13488155
• ISSN: 03854221
• NDL BIB ID: 9531968
• Web Site: https://ndlsearch.ndl.go.jp/books/R000000004-I9531968
• Web Site: http://www.jstage.jst.go.jp/article/ieejeiss/128/6/128_6_919/_pdf
• Text Lang: ja
• Data Source:
  • JaLC
  • NDL
  • Crossref
  • CiNii Articles
• Abstract License Flag: Disallowed