繰り返し演算向け高速剰余乗算器の構成法 [in Japanese] Structure of High-Speed Modulo Multiplier Suitable for Repeated Operations [in Japanese]
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In this paper, we propose a new modulo multiplier suitable for repeated operations using redundant representations. First, we consider a computation rule for radix-2 modulo multiplications. In radix-2 operation, we show two methods to calculate (2<sup><i>i</i>-1</sup> mod <i>n</i>) from (2<sup>i</sup> mod <i>n</i>) and decide product digits sequentially from upper side. These methods make it possible to perform (2<sup><i>i</i>-1</sup> mod <i>n</i>) and multiplications simultaneously. Second, we attempt to apply these methods to radix-4 operations which enables us to reduce clock cycles by only shift and sign change. We propose some structures to perform each part efficiently for radix-4 modulo multiplications. The high-speed redundant binary adder/subtractor which we have already proposed is applied to these structures. By using this adder/subtractor, the longest delay path of this modulo multiplier becomes very short. Finally, by using PARTHENON which is a design system for VLSI, this modulo multiplier is designed and evaluated. As a result, we show the speed of this proposed modulo multiplier becomes over 2.5 times as compared with the conventional structures.
- IEEJ Transactions on Electronics, Information and Systems
IEEJ Transactions on Electronics, Information and Systems 128(6), 933-942, 2008-06-01
The Institute of Electrical Engineers of Japan