An All-Digital PLL for Frequency Multiplication by 4 to 1022 With Seven-Cycle Lock Time

• WATANABE T.

収録刊行物

• IEEE J. Solid-State Circuits

  IEEE J. Solid-State Circuits 38 (2), 198-204, 2003

詳細情報

• CRID: 1572543025454000512
• NII論文ID: 10021133255
• データソース種別:
  • CiNii Articles