多相クロック分周器に基づく低ジッタ特性の分周比可変型ディジタルＰＬＬ

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タイトル別名
  • A Dividing Ratio Changeable Digital PLL with Low Jitter Using a Multiphase Clock Divider
  • タソウ クロック ブンシュウキ ニ モトズク テイジッタ トクセイ ノ ブンシュウヒ カヘンガタ ディジタル PLL

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Since a phase locked loop (PLL) is used in the clock extraction of digital communication and high-density digital recording, it is required to have simultaneously low jitter, fast pull-in, and wide lock-in range characteristics. However, in the case of the conventional dividing ratio changeable digital PLL based on phase state memory and double clock-edge detection (PM-DCPLL), the output jitter in the steady state becomes no less than the half pulse width of the base clock controlling the loop, and the upper bound frequency of lock-in range is limited accordingly.<br>In this paper, we propose the dividing ratio changeable digital phase locked loop (MC-DCPLL) with low jitter, wide lock-in range and fast pull-in characteristics using the multi-phase clock divider. Since the output jitter of this circuit is the 1 phase difference of the multi-phase clock in a steady state. The circuit can thus reduce the output jitter to 1/k of that of conventional PM-DCPLL when the k phase clock is used. Therefore, the upper bound frequency becomes k times as high as that of conventional PM-DCPLL. Furthermore, the initial pull-in is completed in one period of the input signal by using the initial pull-in circuit.

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