書誌事項
- タイトル別名
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- Low Power Active Inductor Using Symmetrical Structure
- アクティブインダクタ ノ タイショウ コウセイ ニ ヨル テイショウヒ デンリョクカ
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This paper proposes power-consumption and chip-area reduction technique for OTA-C based active inductors. In the proposed technique a conventional floating active inductor is divided into two identical active inductors whose chip-size and power consumption are half of the original one. The two divided active inductors are connected in parallel. In the parallel connection opposite ends of the two divided active inductors are connected. Thanks to this modification two pairs of OTAs can be merged and the total number of OTAs is minimized. The proposed technique ideally achieves 33 % reduction in power consumption and more than 33 % reduction in chip-area of the conventional active inductor. Moreover, the proposed active inductor has low mismatch characteristics because it is perfectly symmetrical. It is also shown that the proposed technique is vely effective in low power design of a pair of active inductors for fully balanced circuits.
収録刊行物
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- 電気学会論文誌C(電子・情報・システム部門誌)
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電気学会論文誌C(電子・情報・システム部門誌) 129 (8), 1534-1540, 2009
一般社団法人 電気学会
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詳細情報 詳細情報について
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- CRID
- 1390282679580503040
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- NII論文ID
- 10025101676
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- NII書誌ID
- AN10065950
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- ISSN
- 13488155
- 03854221
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- NDL書誌ID
- 10395934
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- 本文言語コード
- ja
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- データソース種別
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- JaLC
- NDL
- Crossref
- CiNii Articles
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- 抄録ライセンスフラグ
- 使用不可