Power Minimization for Dual- and Triple-Supply Digital Circuits via Integer Linear Programming

• AHN Ki-Yong

  School of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology (KAIST)

• KYUNG Chong-Min

  School of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology (KAIST)

抄録

This paper proposes an Integer Linear Programming (ILP)-based power minimization method by partitioning into regions, first, with three different V_DD's(PM3V), and, secondly, with two different V_DD's(PM2V). To reduce the solving time of triple-V_DD case (PM3V), we also proposed a partitioned ILP method(p-PM3V). The proposed method provides 29% power saving on the average in the case of triple-V_DD compared to the case of single V_DD. Power reduction of PM3V compared to Clustered Voltage Scaling (CVS) was about 18%. Compared to the unpartitioned ILP formulation(PM3V), the partitioned ILP method(p-PM3V) reduced the total solution time by 46% at the cost of additional power consumption within 1.3%.

収録刊行物

• IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E92-A (9), 2318-2325, 2009

  一般社団法人 電子情報通信学会

キーワード

• system on chip
• low power design
• partitioning
• integer linear programming

詳細情報

• CRID: 1390282681287757440
• NII論文ID: 10026859738
• NII書誌ID: AA10826239
• DOI: 10.1587/transfun.e92.a.2318
• ISSN: 17451337
• ISSN: 09168508
• Web Site: http://www.jstage.jst.go.jp/article/transfun/E92.A/9/E92.A_9_2318/_pdf
• 本文言語コード: en
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