A System-Level Model of Design Space Exploration for a Tile-Based 3D Graphics SoC Refinement

    • CHEN Liang-Bi
    • Department of Computer Science and Engineering, National Sun Yat-Sen University
    • YEH Chi-Tsai
    • Department of Information Management, Shih-Chien University
    • CHEN Hung-Yu
    • Department of Computer Science and Engineering, National Sun Yat-Sen University
    • HUANG Ing-Jer
    • Department of Computer Science and Engineering, National Sun Yat-Sen University

抄録

3D graphics application is widely used in consumer electronics which is an inevitable tendency in the future. In general, the higher abstraction level is used to model a complex system like 3D graphics SoC. However, the concerned issue is that how to use efficient methods to traverse design space hierarchically, reduce simulation time, and refine the performance fast. This paper demonstrates a system-level design space exploration model for a tile-based 3D graphics SoC refinement. This model uses UML tools which can assist designers to traverse the whole system and reduces simulation time dramatically by adopting SystemC. As a result, the system performance is improved 198% at geometry function and 69% at rendering function, respectively.

収録刊行物

IEICE transactions on fundamentals of electronics, communications and computer sciences  

IEICE transactions on fundamentals of electronics, communications and computer sciences 92(12), 3193-3202, 2009-12-01 

(社)電子情報通信学会

参考文献:  28件

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各種コード

  • NII論文ID(NAID) :
    10026861675
  • NII書誌ID(NCID) :
    AA10826239
  • 本文言語コード :
    ENG
  • 資料種別 :
    ART
  • ISSN :
    09168508
  • 収録DB :
    CJP書誌  J-STAGE