Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism

Abstract

A novel method to efficiently synthesize hardware from a large behavioral description in behavioral synthesis is proposed. For a program with functions executable in parallel, this proposed method determines a behavioral partitioning which simultaneously minimizes the overall datapath area and the complexity of the controller while maximizing performance of a synthesized circuit by fully exploiting function-level parallelism of a behavioral description. This method is formulated as an integer programming problem. Experimental results demonstrate that this method leads to a shift of the explorable design space so that superior solutions which could not be explored by earlier work are included, showing the effectiveness of our proposed method.

Journal

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences  

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 93(2), 488-499, 2010-02-01 

The Institute of Electronics, Information and Communication Engineers

References:  24

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Codes

  • NII Article ID (NAID) :
    10026863256
  • NII NACSIS-CAT ID (NCID) :
    AA10826239
  • Text Lang :
    ENG
  • Article Type :
    ART
  • ISSN :
    09168508
  • Databases :
    CJP  IR  J-STAGE 

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