Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism

抄録

A novel method to efficiently synthesize hardware from a large behavioral description in behavioral synthesis is proposed. For a program with functions executable in parallel, this proposed method determines a behavioral partitioning which simultaneously minimizes the overall datapath area and the complexity of the controller while maximizing performance of a synthesized circuit by fully exploiting function-level parallelism of a behavioral description. This method is formulated as an integer programming problem. Experimental results demonstrate that this method leads to a shift of the explorable design space so that superior solutions which could not be explored by earlier work are included, showing the effectiveness of our proposed method.

収録刊行物

IEICE transactions on fundamentals of electronics, communications and computer sciences  

IEICE transactions on fundamentals of electronics, communications and computer sciences 93(2), 488-499, 2010-02-01 

Institute of Electronics, Information and Communication Engineers

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各種コード

  • NII論文ID(NAID) :
    10026863256
  • NII書誌ID(NCID) :
    AA10826239
  • 本文言語コード :
    ENG
  • 資料種別 :
    ART
  • ISSN :
    09168508
  • 収録DB :
    CJP書誌  IR  J-STAGE