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In this paper, a cost-efficient LDPC decoder for DVB-S2 is presented. Based on the Normalized Min-Sum algorithm and the turbo-decoding message-passing (TDMP) algorithm, a dual line-scan scheduling is proposed to enable hardware reusing. Furthermore, we present the solution to the address conflict issue caused by the characteristic of the parity-check matrix defined by DVB-S2 LDPC codes. Based on SMIC 0.13µm standard CMOS process, the LDPC decoder has an area of 12.51mm2. The required operating frequency to meet the throughput requirement of 135Mbps with maximum iteration number of 30 is 105MHz. Compared with the latest published DVB-S2 LDPC decoder, the proposed decoder reduces area cost by 34%.
- IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 93(8), 1415-1424, 2010-08-01
The Institute of Electronics, Information and Communication Engineers