A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications

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  • ZHOU Jinjia
    Graduate School of Information, Production and Systems, Waseda University
  • ZHOU Dajiang
    Graduate School of Information, Production and Systems, Waseda University
  • HE Xun
    Graduate School of Information, Production and Systems, Waseda University
  • GOTO Satoshi
    Graduate School of Information, Production and Systems, Waseda University

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In this paper, VLSI architecture of a joint parameter decoder is proposed to realize the calculation of motion vector (MV), intra prediction mode (IPM) and boundary strength (BS) for ultra high definition H.264/AVC applications. For this architecture, a 64-cycle-per-MB pipeline with simplified control modes is designed to increase system throughput and reduce hardware cost. Moreover, in order to save memory bandwidth, the data which includes the motion information for the co-located picture and the last decoded line, is pre-processed before being stored to DRAM. A partition based storage format is applied to condense the MB level data, while variable length coding based compression method is utilized to reduce the data size in each partition. Experimental results show our design is capable of real-time 3840×2160@60fps decoding at less than 133MHz, with 37.2k logic gates. Meanwhile, by applying the proposed scheme, 85-98% bandwidth saving is achieved, compared with storing the original information for every 4×4 block to DRAM.

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