Fixed-Width Group CSD Multiplier Design

• KIM Yong-Eun

  Vehicle-IT Fusion Research Center, Korea Automotive Technology Institute

• CHO Kyung-Ju

  Korea Association of Aids to Navigation (KAAN)

• CHUNG Jin-Gyun

  Division of Electronic Eng., and Information and Communication Research Center, Chonbuk National University

• HUANG Xinming

  Dept. of Electrical & Computer Engr., Worcester Polytechnic Institute

抄録

This paper presents an error compensation method for fixed-width group canonic signed digit (GCSD) multipliers that receive a W-bit input and generate a W-bit product. To efficiently compensate for the truncation error, the encoded signals from the GCSD multiplier are used for the generation of the error compensation bias. By Synopsys simulations, it is shown that the proposed method leads to up to 84% reduction in power consumption and up to 78% reduction in area compared with the fixed-width modified Booth multipliers.

収録刊行物

• IEICE Transactions on Information and Systems

  IEICE Transactions on Information and Systems E93-D (6), 1497-1503, 2010

  一般社団法人 電子情報通信学会

キーワード

• fixed-width
• GCSD multiplier
• quantization error
• digital arithmetic

詳細情報

• CRID: 1390001204379371520
• NII論文ID: 10027987800
• NII書誌ID: AA10826272
• DOI: 10.1587/transinf.e93.d.1497
• ISSN: 17451361
• ISSN: 09168532
• Web Site: http://www.jstage.jst.go.jp/article/transinf/E93.D/6/E93.D_6_1497/_pdf
• 本文言語コード: en
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• 抄録ライセンスフラグ: 使用不可