Optimized 2-D SAD Tree Architecture of Integer Motion Estimation for H.264/AVC

• FAN Yibo

  State Key Lab. of ASIC & System, Fudan University

• ZENG Xiaoyang

  State Key Lab. of ASIC & System, Fudan University

• GOTO Satoshi

  IPS, Waseda University

抄録

Integer Motion Estimation (IME) costs much computation in H.264/AVC video encoder. 2-D SAD tree IME architecture provides very high performance for encoder, and it has been used by many video codec designs. This paper proposes an optimized hardware design of 2-D SAD tree IME. Firstly, a new hardware architecture is proposed to reduce on-chip memory size. Secondly, a new search pattern is proposed to fully use memory bandwidth and reduce external memory access. Thirdly, the data-path is redesigned, and the performance is greatly improved. In order to compare with other IME designs, an IME design support D1 size, 30fps with search range [±32, ±32] is implemented. The hardware cost of this design includes 118 KGates and 8Kb SRAM, the maximum clock frequency is 200MHz. Compared to the original 2-D SAD tree IME, our design saves 87.5% on-chip memory, and achieves 3 times performance than original one. Our design provides a new way to design a low cost and high performance IME for H.264/AVC encoder.

収録刊行物

• IEICE Transactions on Electronics

  IEICE Transactions on Electronics E94-C (4), 411-418, 2011

  一般社団法人 電子情報通信学会

キーワード

• IME
• VBSME
• 2-D SAD tree
• H.264

詳細情報

• CRID: 1390001204375275392
• NII論文ID: 10029505310
• NII書誌ID: AA10826283
• DOI: 10.1587/transele.e94.c.411
• ISSN: 17451353
• ISSN: 09168524
• Web Site: http://www.jstage.jst.go.jp/article/transele/E94.C/4/E94.C_4_411/_pdf
• 本文言語コード: en
• データソース種別:
  • JaLC
  • Crossref
  • CiNii Articles
• 抄録ライセンスフラグ: 使用不可