A Novel Cache Replacement Policy via Dynamic Adaptive Insertion and Re-Reference Prediction

• ZHANG Xi

  Tsinghua National Laboratory for Information Science and Technology, and Department of Computer Science and Technology, Tsinghua University

• LI Chongmin

  Tsinghua National Laboratory for Information Science and Technology, and Department of Computer Science and Technology, Tsinghua University

• LIU Zhenyu

  Tsinghua National Laboratory for Information Science and Technology, and Department of Computer Science and Technology, Tsinghua University

• WANG Haixia

  Tsinghua National Laboratory for Information Science and Technology, and Department of Computer Science and Technology, Tsinghua University

• WANG Dongsheng

  Tsinghua National Laboratory for Information Science and Technology, and Department of Computer Science and Technology, Tsinghua University

• IKENAGA Takeshi

  Graduate School of Information, Production and Systems, Waseda University

抄録

Previous research illustrates that LRU replacement policy is not efficient when applications exhibit a distant re-reference interval. Recently RRIP policy is proposed to improve the performance for such kind of workloads. However, the lack of access recency information in RRIP confuses the replacement policy to make the accurate prediction. To enhance the robustness of RRIP for recency-friendly workloads, we propose an Dynamic Adaptive Insertion and Re-reference Prediction (DAI-RRP) policy which evicts data based on both re-reference prediction value and the access recency information. DAI-RRP makes adaptive adjustment on insertion position and prediction value for different access patterns, which makes the policy robust across different workloads and different phases. Simulation results show that DAI-RRP outperforms LRU and RRIP. For a single-core processor with a 1MB 16-way set last-level cache (LLC), DAI-RRP reduces CPI over LRU and Dynamic RRIP by an average of 8.1% and 2.7% respectively. Evaluations on quad-core CMP with a 4MB shared LLC show that DAI-RRP outperforms LRU and Dynamic RRIP (DRRIP) on the weighted speedup metric by an average of 8.1% and 15.7% respectively. Furthermore, compared to LRU, DAI-RRP consumes the similar hardware for 16-way cache, or even less hardware for high-associativity cache. In summary, the proposed policy is practical and can be easily integrated into existing hardware approximations of LRU.

収録刊行物

• IEICE Transactions on Electronics

  IEICE Transactions on Electronics E94-C (4), 468-476, 2011

  一般社団法人 電子情報通信学会

キーワード

• cache replacement
• set dueling
• adaptive insertion
• shared cache

詳細情報

• CRID: 1390001204375271040
• NII論文ID: 10029505401
• NII書誌ID: AA10826283
• DOI: 10.1587/transele.e94.c.468
• ISSN: 17451353
• ISSN: 09168524
• Web Site: http://www.jstage.jst.go.jp/article/transele/E94.C/4/E94.C_4_468/_pdf
• 本文言語コード: en
• データソース種別:
  • JaLC
  • Crossref
  • CiNii Articles
  • KAKEN
• 抄録ライセンスフラグ: 使用不可