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- KIM Kyundong
- Graduate School of Engineering, The University of Tokyo
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- TAKEDA Seidai
- Graduate School of Engineering, The University of Tokyo
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- MIWA Shinobu
- Graduate School of Information Science and Technology, The University of Tokyo
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- NAKAMURA Hiroshi
- Graduate School of Engineering, The University of Tokyo Graduate School of Information Science and Technology, The University of Tokyo
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抄録
Caches are one of the most leakage consuming components in modern processor because of massive amount of transistors. To reduce leakage power of caches, several techniques using power-gating (PG) were proposed. Despite of its high leakage saving, a side effect of PG for caches is the loss of data during a sleep. If useful data is lost in sleep mode, it should be fetched again from a lower level memory. This consumes a considerable amount of energy, which very unfortunately mitigates the leakage saving. This paper proposes a new PG scheme considering data retentiveness of SRAM. After entering the sleep mode, data of an SRAM cell is not lost immediately and is usable by checking the validity of the data. Therefore, we utilize data retentiveness of SRAM to avoid energy overhead for data recovery, which results in further chance of leakage saving. To check availability, we introduce a simple hardware whose overhead is ignorable. Our experimental result shows that utilizing data retentiveness saves up to 32.42% of more leakage than conventional PG.
収録刊行物
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- IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E95.A (12), 2301-2308, 2012
一般社団法人 電子情報通信学会
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詳細情報 詳細情報について
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- CRID
- 1390001206312002944
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- NII論文ID
- 10031161364
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- NII書誌ID
- AA10826239
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- ISSN
- 17451337
- 09168508
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- 本文言語コード
- en
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- データソース種別
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- JaLC
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- 使用不可