B24-072 STRESS-OPTIMIZATION DESIGN OF A THIN-FILM SEMICONDUCTOR DEVICE :

• KUMAGAI,YUKIHIRO

  Mechanical Engineering Research Laboratory, Hitachi, Ltd.

• OHTA,HIROYUKI

  Mechanical Engineering Research Laboratory, Hitachi, Ltd.

• MIURA,HIDEO

  Tohoku University

• SHIMIZU,AKIHIRO

  Hitachi ULSI Systems, Co.

抄録

A stress-design technique for semiconductor devices was developed. This technique consists of a database-construction system, a stress-evaluation system, and a stress-simulation system. And it was used to improve the drain-current characteristic of a MOSFET. The stress simulation showed that the stress in the channel of the MOSFET was sensitive to the stress in a SIN film, which was deposited over the MOSFET. And the SiN film stress dependence of the drain current was experimentally clarified. In order to control the stress in the SiN film, germanium ions were implanted into the SiN film. As a result of this stress control, the drain current of an n-MOSFET increased by 13% without reducing that of a p-MOSFET.

収録刊行物

• International Symposium on Micro-Mechanical Engineering : ISMME

  International Symposium on Micro-Mechanical Engineering : ISMME 2003 427-432, 2003-11-30

  日本機械学会

キーワード

• Stress
• Reliability
• Stress analysis
• MOSFET

詳細情報

• CRID: 1542261570160547328
• NII論文ID: 110002344902
• NII書誌ID: AA11903244
• Web Site: http://dl.ndl.go.jp/info:ndljp/pid/10351121
• 本文言語コード: en
• データソース種別:
  • NDL-Digital
  • CiNii Articles