Architecture of an AI Processor Chip (IP1704)

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著者

    • Mitsuo Saito
    • Information Systems Laboratory, Toshiba Research and Development Center, Toshiba Corporation
    • Takeshi Aikawa
    • Information Systems Laboratory, Toshiba Research and Development Center, Toshiba Corporation
    • Tsukasa Matoba
    • Information Systems Laboratory, Toshiba Research and Development Center, Toshiba Corporation
    • Mitsuyoshi Okamura
    • Information Systems Laboratory, Toshiba Research and Development Center, Toshiba Corporation
    • Kenji Minagawa
    • Information Systems Laboratory, Toshiba Research and Development Center, Toshiba Corporation
    • Tadatoshi Ishii
    • Information and Communication Systems Laboratory, Toshiba Corporation

抄録

The CPU of the AI processor (AIP) called IP704 was developed for Prolog and Lisp based on RISC architecture with hardware supports. It has been proved that IP704 architecture is effective for both AI languages and general-purpose languages. An AI processor chip (IP 1704) is being developed as a direct successor of the IP704. The architecture has been modified and refined to fit onto a single chip and to improve the execution speed. Features newly developed for the IP1704 include Overlapping of the decode and register-read stages using a combination of the hardware decoder and micro-programs and a delayed cache hit check with delayed writing. Is shown that a RISC-based processor with suitable hardware support is applicable to VLSI and also gives high performance AI languages.The CPU of the AI processor (AIP) called IP704 was developed for Prolog and Lisp, based on RISC architecture with hardware supports. It has been proved that IP704 architecture is effective for both AI languages and general-purpose languages. An AI processor chip (IP 1704) is being developed as a direct successor of the IP704. The architecture has been modified and refined to fit onto a single chip and to improve the execution speed. Features newly developed for the IP1704 include Overlapping of the decode and register-read stages using a combination of the hardware decoder and micro-programs, and a delayed cache hit check with delayed writing. Is shown that a RISC-based processor with suitable hardware support is applicable to VLSI and also gives high performance AI languages.

The CPU of the AI processor (AIP) called IP704 was developed for Prolog and Lisp, based on RISC architecture with hardware supports. It has been proved that IP704 architecture is effective for both AI languages and general-purpose languages. An AI processor chip (IP 1704) is being developed as a direct successor of the IP704. The architecture has been modified and refined to fit onto a single chip and to improve the execution speed. Features newly developed for the IP1704 include Overlapping of the decode and register-read stages using a combination of the hardware decoder and micro-programs, and a delayed cache hit check with delayed writing. Is shown that a RISC-based processor with suitable hardware support is applicable to VLSI and also gives high performance AI languages.

収録刊行物

  • Journal of Information Processing

    Journal of Information Processing 13(2), 144-149, 1990-08-25

    一般社団法人情報処理学会

各種コード

  • NII論文ID(NAID)
    110002673519
  • NII書誌ID(NCID)
    AA00700121
  • 本文言語コード
    ENG
  • 資料種別
    Article
  • ISSN
    1882-6652
  • データ提供元
    NII-ELS  IPSJ 
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