Architecture of an AI Processor Chip (IP1704)

    • SAITO MITSUO
    • Information Systems Laboratory, Toshiba Research and Development Center, Toshiba Corporation
    • AIKAWA TAKESHI
    • Information Systems Laboratory, Toshiba Research and Development Center, Toshiba Corporation
    • MATOBA TSUKASA
    • Information Systems Laboratory, Toshiba Research and Development Center, Toshiba Corporation
    • OKAMURA MITSUYOSHI
    • Information Systems Laboratory, Toshiba Research and Development Center, Toshiba Corporation

    • MINAGAWA KENJI
    • Information Systems Laboratory, Toshiba Research and Development Center, Toshiba Corporation
    • ISHII TADATOSHI
    • Information and Communication Systems Laboratory, Toshiba Corporation

Abstract

The CPU of the AI processor (AIP) called IP704 was developed for Prolog and Lisp, based on RISC architecture with hardware supports. It has been proved that IP704 architecture is effective for both AI languages and general-purpose languages. An AI processor chip (IP 1704) is being developed as a direct successor of the IP704. The architecture has been modified and refined to fit onto a single chip and to improve the execution speed. Features newly developed for the IP1704 include Overlapping of the decode and register-read stages using a combination of the hardware decoder and micro-programs, and a delayed cache hit check with delayed writing. Is shown that a RISC-based processor with suitable hardware support is applicable to VLSI and also gives high performance AI languages.

Journal

Journal of information processing   [List of Volumes]

Journal of information processing 13(2), 144-149, 1990-08-25  [Table of Contents]

Information Processing Society of Japan (IPSJ)

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Codes

  • NII Article ID (NAID) :
    110002673519
  • NII NACSIS-CAT ID (NCID) :
    AA00700121
  • Text Lang :
    ENG
  • ISSN :
    03876101
  • Databases :
    NII-ELS 

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