A 32-bit LISP processor for the AI Workstation ELIS with a Multiple Programming Paradigm Language TAO

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Author(s)

    • Hibino Y.
    • Nippon Telegraph and Telephone Corporation Human Interface Laboratories
    • TAKEUCHI IKUO
    • Nippon Telegraph and Telephone Corporation Basic Research Laboratories

Abstract

This paper describes a 32-bit LISP processor chip developed for the AI workstation ELIS with the multiple programming paradigm language TAO. The objective of this microprocessor is to realize an S-expression machine that can match the speed of conventional machines for compiled code execution. Architectural features are a repetitive structure for VLSI implementation of the tagged architecture and a dedicated datapath for list manipulation. All the processor functions are realized on a single VLSI chip that uses a 2-micron CMOS process. ELIS supports not only LISP but also multiple programming paradigms. The ELIS interpreter has a higher performance than that of any other dedicated machine on the market.

Journal

  • Journal of Information Processing  

    Journal of Information Processing 13(2), 156-164, 1990 

    Information Processing Society of Japan (IPSJ)

Cited by:  1

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Codes

  • NII Article ID (NAID)
    110002673521
  • NII NACSIS-CAT ID (NCID)
    AA00700121
  • Text Lang
    ENG
  • Article Type
    Journal Article
  • ISSN
    03876101
  • Data Source
    CJPref 
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