Low-Energy Design Using Datapath Width Optimization for Embedded Processor-Based Systems

• Cao Yun

• Yasuura Hiroto

抄録

This paper presents a novel system-level technique that minimizes the energy consumption of embedded processor-based systems through datapath width optimization. It is based on the idea of minimizing energy consumed by redundant bits, which are unused during execution of programs by means of optimizing the datapath width of processors. To minimize the redundant bits of variables in a given application program, the effective size of each variable is determined by variable size analysis, and Valen-C language is used to preserve the precision of computation. Analysis results of variables show that there are average 39% redundant bits in the C source program of MPEG2 video decoder. In our experiments for several real embedded applications, energy savings without performance penalty are reported and range from about 10.8% to 48.3%.

収録刊行物

• IPSJ Journal

  IPSJ Journal 43 (5), 1348-1356, 2002-05

  IPSJ

キーワード

• 特集：システムLSIの設計技術と設計自動化

詳細情報

• CRID: 1390290699812198784
• NII論文ID: 110002726363
• NII書誌ID: AN00116647
• ISSN: 18827764
• ISSN: 03875806
• DOI: 10.15017/3710
• HANDLE: 2324/6794458
• NDL書誌ID: 6161541
• Web Site: http://id.nii.ac.jp/1001/00011645/
• Web Site: https://ndlsearch.ndl.go.jp/books/R000000004-I6161541
• 本文言語コード: en
• データソース種別:
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  • IRDB
  • NDL
  • CiNii Articles