高速補助記憶装置を使用したミニコン用LISP 1.6 システム LISP 1.6 system for a mincomputer using high speed auxiliary core memory

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The implementation of LISP 1.6(LIST processing language 1.6) for a minicomputer (TOSBAC_40C) is described. The implementation of a full-power LISP processor require large program area and large free cell space, because the LISP processor must be able to run a large program efficiently. As our minicomputer has a small main memory, it is required to attach a high speed bulk core memory(512kB) as a virtual memory by the software paging mechanism based on the LRU algorithm. Upon these address spaces, we can use maximum 64k LISP cells. As a processor has the ability to swap out any list expression into the secondary memory in the form of S-expression(Symbolic expression), the user can run a fairly large program that requires more cells than 64k cells for the running. Many other ideas are employed in this processor, such as the data type of the pointer is determined by the address computation (hence the conventional data type flags in the cell are eliminated completely), the shallow binding mechanism is employed as the variable binding, the compaction and linearization of the cells are taken place at the garbage collection, and the processor works under the disk operating system. As this processor has so many features, it is easy to use, and a large LISP program is run-nable efficiently.

収録刊行物

  • 情報処理

    情報処理 17(8), 720-728, 1976-08-15

    一般社団法人情報処理学会

各種コード

  • NII論文ID(NAID)
    110002753335
  • NII書誌ID(NCID)
    AN00116625
  • 本文言語コード
    JPN
  • 資料種別
    Departmental Bulletin Paper
  • ISSN
    04478053
  • データ提供元
    NII-ELS  IPSJ 
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