A 1.1 M LIPS (i.e. MHz) Flat GHC Interpreter for the Hitachi Supercomputer S-820

Abstract

We will describe some optimizations of an implementation of Flat GHC For the Hitachi S-820/80 supercomputer. The implementation performs about 1.1 million process reductions per second, for a concatenate-type benchmark.

Journal

全国大会講演論文集   [List of Volumes]

全国大会講演論文集 第37回昭和63年後期(1), 687-688, 1988-09-12  [Table of Contents]

Information Processing Society of Japan (IPSJ)

Preview

Preview

Codes

  • NII Article ID (NAID) :
    110002895184
  • NII NACSIS-CAT ID (NCID) :
    AN00349328
  • Text Lang :
    ENG
  • Databases :
    NII-ELS