A Simultaneous Placement ang Global Routing Algorithm for Transport-Processing FPGAs

• TOGAWA Nozomu

  Dept. of Electronics and Communication Engineering Waseda University

• SATO Masao

  Dept. of Electronics and Communication Engineering Waseda University

• OHTSUKI Tatsuo

  Dept. of Electronics and Communication Engineering Waseda University

Bibliographic Information

Other Title

• 通信処理用FPGAを対象とした配置 概略配線同時処理手法

Abstract

This paper proposes a simultaneous placement and global routing algorithm for transport-processing FPGAs whose primary objective is minimizing routing congestion. The algorithm is based on hierarchical bipartition of layout regions and sets of LUTs (LookUp Tables) to be placed. It achieves bipartitioning which leads to small routing congestion by applying a network flow technique to it and computing a maximum flow and a minimum cut. If there exist connections between bipartitioned LUT sets, pairs of pseudo-terminals are introduced to preserve the connections. A sequence of pseudo-terminals represents a global route of each net. As a result, both placement of LUTs and global routing are determined when hierarchical bipartitioning procedures are finished. The experimental results for practical transport-processing circuits show its efficiency and effectiveness.

Journal

• IPSJ SIG Notes

  IPSJ SIG Notes 15-22, 1996

  Information Processing Society of Japan (IPSJ)

Keywords

• transport-processing FPGA
• layout design
• placement
• global routing
• network flow

Details

• CRID: 1573668926989369088
• NII Article ID: 110002930527
• NII Book ID: AN1011091X
• Text Lang: ja
• Data Source:
  • CiNii Articles