電子ビーム吸収電流解析によるLSI配線の不良位置特定(LSIシステムの実装・モジュール化技術及びテスト技術,一般)  [in Japanese] Fault Localization in LSI-interconnects using Electron Beam Absorbed Current Analysis  [in Japanese]

LSIの微細化・多層化に伴い、困難になりつつある配線やビアの不良位置特定を目的に、電子ビームの集束性と透過性を活用した電子ビーム吸収電流解析装置を開発した。本装置は、汎用SEMとφ200ウエハ対応ステージ、メカニカルプローブ、電流アンプ、マーキング機構で構成される。本装置をTEGおよび製品の解析に適用し、以下のことを確認した。1)試料最表面から5um下までの配線が解析可能2)解析可能な不良抵抗値は2×10^4Ω以上3)製品解析の場合、ネット出力部に強いEBIC反応が生じ、不良ネット解析に活用可能14)不良位置に形成したマークは、FIBに対する視認性および耐久性は良好

It is getting to be difficult more and more to locate fault sites in LSI devices, because of its fine pitch wiring and multi-layer structure. We developed a fault localizing system using fine focused electron beam penetrating and absorbed in wires of LSI devices. This system consists of cold field emission scanning electron microscope, 8' wafer stage, mechanical probing mechanism, current amplifier and EBCVD (= Electron Beam Chemical Vapor Deposition) marking utility. The performance of this system is investigated using TEG (= Test Element Group) and fabrication finished LSI as samples. The results are as follows. 1) Wires placed Sum below sample surface can be analyzed. 2) The detectable resistance of faults is over 2E+4 ohm. 3) In the case of finished LSI, strong EBIC (=Electron Beam Induced Current) reactions are detected in CMOS output area. The reaction can be utilized for an actual analysis. 4) Marks formed by EBCVD at fault sites are tolerant against the irradiation of FIB (=Focused Ion Beam), and can be clearly recognized in SIM (=Scanning Ion Microscope) image.