New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency

As opposed to scan schemes, non-scan DFT allows at-speed testing. This paper suggests three techniques on non-scan DFT of sequential circuits. The novelty of the proposed techniques is that by using combinational ATPG tool 100% fault efficiency is guaranteed. Test sequences are generated from test patterns obtained by ATPG tool on the combinational part of the sequential machine. In all techniques, an additional circuit to reach invalid states (CRIS) is proposed to reach unreachable states on the state register of a machine. The second and third technique use an additional hardware called differentiating logic (DL), which uniquely identify a state appearing in a state register. The design of this DL is universal, i.e., not dependent on the circuit structure. Hardware overhead of DL and CRIS is lower than that of full scan. Test generation and test application time are also found to compare favorably to those of earlier designs.