Design of the Shared-Buffering ATM Switch LSI chipset using 0.5-μm CMOS technology

• SASAKI Yasuhito

  Information Technology R&D Center, Mitsubishi Electric Corporation

• YAMANAKA Hideaki

  Information Technology R&D Center, Mitsubishi Electric Corporation

• KONDOH Harufusa

  System LSI Laboratory, Mitsubishi Electric Corporation

• SAITO Hirotaka

  Information Technology R&D Center, Mitsubishi Electric Corporation

• TSUZUKI Munenori

  Information&Communication, Mitsubishi Electric Corporation

• KOHAMA Shigeki

  Communication Equipment Works, Mitsubishi Electric Corporation

• YAMADA Hirotoshi

  Information Technology R&D Center, Mitsubishi Electric Corporation

• MATSUDA Yoshio

  System LSI Laboratory, Mitsubishi Electric Corporation

• OSHIMA Kazuyoshi

  Information&Communication, Mitsubishi Electric Corporation

Bibliographic Information

Other Title

• 0.5μm CMOS技術による共通バッファ形ATMスイッチのLSI構成

Abstract

A newly proposed funnel-structured expandable architecture in the shared buffer type ATM switch and a searchable address queueing scheme are presented. The funnel structure gives flexible capability to build up various sizes of ATM switches. The searchable address queue, in which all the addresses of the stored cells for different output ports are queued in single-FIFO hardware, can reduce the total memory capacity drastically and enables the address queue to be contained inside the LSI chip. This technique has also great advantage for implementing the mulicast and multilevel priority-control functions.

Journal

• IEICE technical report. Information networks

  IEICE technical report. Information networks 95 (267), 37-42, 1995-09-29

  The Institute of Electronics, Information and Communication Engineers

Keywords

• 0.5-μm CMOS technology
• shared buffering
• ATM switch
• LSI
• multicast
• priority control

Details

• CRID: 1572543027237377920
• NII Article ID: 110003196066
• NII Book ID: AN10013072
• Text Lang: ja
• Data Source:
  • CiNii Articles