Thread Composition Method for Hardware Compiler Bach Maximizing Resource Sharing among Processes

• TAKAHASHI Mizuki

  the Design Technology Development Laboratory, Integrated Circuits Development Group, SHARP Corporation

• ISHIURA Nagisa

  the Graduate School of Engineering, Osaka University

• YAMADA Akihisa

  the Design Technology Development Laboratory, Integrated Circuits Development Group, SHARP Corporation

• KAMBE Takashi

  the Design Technology Development Laboratory, Integrated Circuits Development Group, SHARP Corporation

抄録

This paper presents a method of thread composition in a hardware compiler Bach. Bach synthesizes RT level circuits from a system description written in Bach-C language, where a system is modeled as communicating processes running in parallel. The system description is decomposed into threads, i.e., strings of sequential processes, by grouping processes which are not executed in parallel. The set of threads are then converted into behavioral VHDL models and passed to a behavioral synthesizer. The proposed method attempts to find a thread configuration that maximize resource sharing among processes in the threads. Experiments on two real designs show that the circuit sizes were reduced by 3.7% and 14.7%. We also show the detailed statistics and analysis of the size of the resulting gate level circuits.

収録刊行物

• IEICE transactions on fundamentals of electronics, communications and computer sciences

  IEICE transactions on fundamentals of electronics, communications and computer sciences 83 (12), 2456-2463, 2000-12-01

  一般社団法人電子情報通信学会

キーワード

• behavioral partitioning
• thread composition
• behavioral synthesis

詳細情報

• CRID: 1573668927147706240
• NII論文ID: 110003208490
• NII書誌ID: AA10826239
• ISSN: 09168508
• 本文言語コード: en
• データソース種別:
  • CiNii Articles